System and method for automatically saving memory contents of a data processing device on power failure

• US 20060072369A1
• Filed: 10/12/2004
• Published: 04/06/2006
• Est. Priority Date: 10/04/2004
• Status: Active Grant

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Research In Motion Limited (Blackberry Limited)
• Inventors: Madter, Richard C., Huang, Wei Yao, Werder, Karin Alicia
• Granted Patent: US 7,634,688 B2
• Time in Patent Office: Days
• US Class Current: 365/232
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method for automatically saving the contents of volatile memory in a data processing device on power failure. A secondary power supply is provided, which upon failure of the primary power supply supplies power long enough for all modified information stored in volatile memory to be written to a non-volatile memory device such as NAND flash in an AutoSave procedure. In the preferred embodiment modified sectors in volatile memory are flagged, and only modified sectors with a directory list are written to non-volatile memory during the AutoSave procedure.

Claims

1. A method of automatically saving data upon interruption of power from a primary power supply in a data processing device having a non-volatile memory device for storing data and retaining the stored data when the primary power supply is deactivated and a volatile memory device for caching data from the non-volatile memory device for reading or processing by a processor when the primary power supply is activated, comprising the steps of:

a. designating modified sectors of data stored in the volatile memory device as modified and storing a modified sector directory list,

b. detecting a power interruption in the primary power supply,

c. enabling a secondary power supply, and

d. writing data from the volatile memory device and the modified data directory list to the non-volatile memory device while the secondary power supply is enabled.

2. The method of claim 1 comprising, in step d., writing only modified data from the volatile memory device and the modified data directory list to the non-volatile memory device.

3. The method of claim 2 comprising, before step b., the step of detecting when a predetermined limit of modified data has been reached or exceeded and writing data from the volatile memory device to the non-volatile memory device to reduce the number of modified data sectors to below the predetermined limit.

4. The method of claim 2 wherein the non-volatile memory comprises a NAND flash memory device.

5. The method of claim 4 comprising, before step b. maintaining at least one sector address register pointing to at least one erased block in non-volatile memory for writing data in step d.

6. The method of claim 5 comprising maintaining at least one sector address register pointing to a group of erased blocks.

7. The method of claim 5 wherein the at least one sector address register can be configured to point to one erased block or to a group of erased blocks.

8. The method of claim 2 wherein, before step b., when a possible interruption in the primary power supply is detected modified data is written to the non-volatile memory device before power from the primary power supply is interrupted.

9. In a data processing device having a primary power supply, a non-volatile memory device for storing data and retaining the stored data when the primary power supply is deactivated, and a volatile memory device for storing data from the non-volatile memory device for reading or processing by a processor when the primary power supply is activated, an automatic data saving system comprising

a memory controller component for controlling a flow of data between the non-volatile memory device and the volatile memory device and storing a modified sector directory list,

a tracking component for designating sectors of modified data stored in the volatile memory device as modified,

a detection component for detecting a power interruption in the primary power supply, and

a secondary power supply enabled upon detection of a power interruption in the primary power supply, providing electrical power sufficient to allow for modified data sectors in the volatile memory device to be written to the non-volatile memory device.

10. The automatic data saving system of claim 9 wherein the tracking component assigns a tag to designate data stored in the volatile memory device as modified.

11. The automatic data saving system of claim 10 wherein upon detection of a power interruption only modified data from the volatile memory device and the modified sector directory list information is written to the non-volatile memory device.

12. The automatic data saving system of claim 11 comprising a counter for detecting when a predetermined limit of modified data has been reached or exceeded, wherein before detection of a power interruption data is written from the volatile memory device to the non-volatile memory device to reduce the number of modified data sectors to below the predetermined limit.

13. The automatic data saving system of claim 10 wherein the non-volatile memory comprises a NAND flash memory device.

14. The automatic data saving system of claim 13 wherein the volatile memory comprises an SDRAM memory device.

15. The automatic data saving system of claim 13 comprising at least one sector address register pointing to at least one erased block in non-volatile memory for writing data upon detection of a power interruption.

16. The automatic data saving system of claim 15 comprising at least one sector address register pointing to a group of erased blocks.

17. The automatic data saving system of claim 15 wherein the at least one sector address register can be configured to point to one erased block or to a group of erased blocks.

18. The automatic data saving system of claim 10 comprising a pre-interrupt saving procedure whereby when a possible interruption in the primary power supply is detected modified data is written to the non-volatile memory device before power from the primary power supply is interrupted.