Packet processing

• US 20060072563A1
• Filed: 10/05/2004
• Published: 04/06/2006
• Est. Priority Date: 10/05/2004
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Newell, Donald, Illikkal, Ramesh G., Iyer, Ravishankar, Makineni, Srihari, McAlpine, Gary L., Huggahalli, Ram, Minturn, David B., Regnier, Greg J., Saletore, Vikram A.
• Application Number:
  US10/959,488
• Publication Number:
  US 20060072563A1
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

In general, the disclosure describes a variety of techniques that can enhance packet processing operations.

Claims

1. A system, comprising:

at least one processor including at least one respective cache;

at least one interface to at least one randomly accessible memory; and

circuitry to, in response to a processor request, independently copy data from a first set of locations in the randomly accessible memory to a second set of locations in the randomly accessible memory;

at least one network interface, the network interface comprising circuitry to;

signal to the at least one processor after receipt of packet data; and

initiate storage in the at least one cache of the at least one processor of at least a portion of the packet data, wherein the storage of the at least a portion of the packet data is not solicited by the processor;

instructions disposed on an article of manufacture, the instructions to cause the at least one processor to provide multiple threads of execution to process packets received by the network interface controller, individual threads including instructions to;

yield execution by the at least one processor at multiple points within the thread'"'"'s flow of execution to a different one of the threads;

fetch data into the at one least one cache of the at least one processor before subsequent instructions access the fetched data;

initiate, by the circuitry to independently copy data, a copy of at least a portion of a packet received by the network interface controller from a first set of locations in the randomly accessible memory to a second set of locations in the at least one randomly accessible memory.

2. The system of claim 1, wherein the network interface circuitry further comprises circuitry to perform a hash operation on at least a portion of a received packet.

3. The system of claim 1, wherein the network interface circuitry further comprises circuitry to perform a checksum of a received packet.

4. The system of claim 1, wherein the network interface circuitry further comprises a packet buffer.

5. The system of claim 1, wherein the circuitry to independently copy data further comprises circuitry to, in response to a processor request, independently copy data from a first set of locations in a randomly accessible memory to a second set of locations in the processor cache;

6. The system of claim 1,

wherein the network interface circuitry comprises circuitry configured to signal the receipt of multiple packets;

and

wherein the instructions of the threads comprise instructions to perform a fetch for multiple ones of the multiple packets.

7. The system of claim 1,

wherein the threads comprise different concurrently active flows of execution control within a single operating system process.

8. The system of claim 1,

wherein the thread instructions comprise instructions to fetch data into the at least one cache comprise at least one instruction to fetch at least a portion of a TCP Transmission Control Block (TCB).

9. The system of claim 8,

wherein the thread instructions comprise instructions to perform a thread yield immediately following execution of the at least one instruction to fetch data.

10. The system of claim 1,

wherein the threads:

(1) maintain a TCP state machine for different connections, (2) generate TCP ACK messages, (3) perform TCP segment reassembly, and (4) determine a TCP window for a TCP connection.

11. The system of claim 1,

wherein the threads features different sets of thread instructions to process Transmission Control Protocol (TCP) control packets and TCP data packets.

12. The system of claim 1, wherein the at least one processor comprises a processor having multiple programmable cores integrated within the same die.

13. A system, comprising:

at least one interface to at least one processor having at least one cache;

at least one interface to at least one randomly accessible memory;

at least one network interface;

circuitry to independently copy data from a first set of locations in a randomly accessible memory to a second set of locations in a randomly accessible memory in response to a command received from the at least one processor; and

circuitry to place data received from the at least one network interface in the at least one cache of the at least one processor.

14. The system of claim 13, wherein the circuitry to place data received from the at least one network interface comprises circuitry to place at least a portion of a packet in the at least one cache of the at least one processor before a processor request to access the data.

15. The system of claim 13, wherein the command received from the at least one processor comprises a source address of a randomly accessible memory and a destination address of the at least one randomly accessible memory.

16. The system of claim 13, wherein the command comprises identification of a target device.

17. The system of claim 13, wherein the processor comprises multiple programmable cores integrated on a single die.

18. The system of claim 13, wherein the processor comprises a processor providing multiple threads of execution.

19. The system of claim 13, further comprising the at least one network interface.

20. The system of claim 13, wherein the network interface comprises circuitry to:

determine a checksum of a received packet;

hash at least a portion of the received packet; and

signal the receipt of data.

21. An article of manufacture comprising instructions that when executed cause a processor to perform operations comprising:

receiving at a processor an indication of receipt of one or more packets; and

if more than one packet was received, fetching at least the headers of multiple ones of the more than one packet into a cache of the processor before instructions executed by the processor operate on all of the headers of the multiples ones of the more than one packet.

22. The article of claim 21,

wherein the one or more packets comprise Transmission Control Protocol/Internet Protocol (TCP/IP) packets;

and

further comprising instructions to perform operations comprising fetching at least one selected from the group of;

(1) a reference to Transmission Control Blocks (TCBs) of the respective TCP/IP packets; and

(2) the TCBs of the respective TCP/IP packets.

23. The article of claim 21, further comprising instructions to perform operations comprising initiating independent copying of a packet payload to an application specified address by memory copy circuitry.

25. The article of claim 23, further comprising instructions that when executed initiate an independent copy operation of a TCP/IP packet payload by copy circuitry asynchronous to a processor executing the multiple threads.

26. The article of claim 23,

wherein the instructions comprise at least two sets of thread instructions to process received Transmission Control Protocol (TCP) segments, the two sets of thread instructions including at least one set of thread instructions to process TCP control segments and at least one set of thread instructions to process TCP data segments;

and

further comprising instructions to perform operations comprising determining whether a TCP segment is a TCP control segment or a TCP data segment.

24. An article of manufacture comprising instructions that when executed cause a processor to perform operations comprising:

providing multiple threads of execution of at least one set of instructions, at least one of the set of instructions comprising;

multiple yields of execution to a different one of the multiple threads;

multiple fetches to load data into a processor cache, the data fetched comprising data selected from the following group;

(1) a reference to a Transmission Control Block (TCB) of a Transmission Control Protocol/Internet Protocol (TCP/IP) packet;

(2) a TCB of a TCP/IP packet; and

(3) a header of a TCP/IP packet.

27. A method comprising:

at a network interface controller;

receiving at least one link layer frame, the link layer frame encapsulating at least one Transmission Control Protocol/Internet Protocol packet;

determining a checksum for the at least one encapsulated Transmission Control Protocol/Internet Protocol packet;

determining a hash based on, at least, a source Internet Protocol address, a destination Internet Protocol address, a source port, and a destination port identified by an Internet Protocol header and a Transmission Control Protocol header of the Transmission Control Protocol/Internet Protocol packet;

signaling an interrupt to at least one processor after receipt of at least a portion of the at least one link layer frame;

initiating placement of, at least, the Internet Protocol header and the Transmission Control Protocol header into a cache of the at least one processor prior to a processor request to access a memory address identifying storage of the Internet Protocol header and the Transmission Control Protocol header;

at circuitry interconnecting the processor, the network interface controller, and at least one randomly accessible memory;

receiving a request from the processor to independently transfer at least a portion of a payload of a Transmission Control Protocol segment from a first set of memory locations in a randomly accessible memory to a second set of memory locations in the at least one randomly accessible memory;

at the processor;

providing multiple threads of execution, wherein individual ones of the multiple threads execute a set of instructions to perform operations that include;

at least one yield of execution to a different one of the multiple threads; and

at least one fetch to load data into a processor cache, the data fetched selected from the following group;

(1) a reference to Transmission Control Blocks (TCBs) of the a Transmission Control Protocol/Internet Protocol (TCP/IP) packet;

(2) the TCB of a TCP/IP packet; and

(3) a header of a TCP/IP packet

28. The method of claim 27, wherein the multiple threads of execution comprise multiple ones of the multiple threads within a same operating system process.

29. The method of claim 27, wherein the request from the processor to independently transfer at least a portion of a payload of a Transmission Control Protocol segment from a first set of memory locations in a randomly accessible memory to a second set of memory locations in the at least one randomly accessible memory caused the payload to be transferred directly to the cache of a processor.

30. A system comprising:

a network interface, the network interface comprising circuitry to;

receive at least one link layer frame, the link layer frame encapsulating at least one Transmission Control Protocol/Internet Protocol packet;

determine a checksum for the Transmission Control Protocol/Internet Protocol packet;

determine a hash based on, at least, a source Internet Protocol address, a destination Internet Protocol address, a source port, and a destination port identified by an Internet Protocol header and a Transmission Control Protocol header of the Transmission Control Protocol/Internet Protocol packet;

signal to at least one processor after receipt of at least a portion of the at least one link layer frame;

initiate placement of, at least, the Internet Protocol header and the Transmission Control Protocol header into a cache of the at least one processor prior to a processor request to access a memory address identifying storage of the Internet Protocol header and the Transmission Control Protocol header;

circuitry interconnecting the processor, the network interface, and at least one randomly accessible memory, the circuitry comprising circuitry to;

receive a request from the processor to independently transfer at least a portion of a payload of a Transmission Control Protocol segment from a first set of memory locations in a randomly accessible memory to a second set of memory locations in the at least one randomly accessible memory;

the processor including the at least one cache; and

an article of manufacture comprising instructions that when executed cause a processor to perform operations comprising;

providing multiple threads of execution, wherein individual ones of the multiple threads execute a set of instructions to perform operations that include;

multiple yields of execution to a different one of the multiple threads; and

multiple fetches to load data into a processor cache, the data fetched selected from the following group;

(1) a reference to Transmission Control Blocks (TCBs) of the a Transmission Control Protocol/Internet Protocol (TCP/IP) packet;

(2) the TCB of a TCP/IP packet; and

a header of a TCP/IP packet

31. The system of claim 30, wherein the multiple threads of execution comprise multiple ones of the multiple threads within a same operating system process.