Packet processing
First Claim
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1. A system, comprising:
- at least one processor including at least one respective cache;
at least one interface to at least one randomly accessible memory; and
circuitry to, in response to a processor request, independently copy data from a first set of locations in the randomly accessible memory to a second set of locations in the randomly accessible memory;
at least one network interface, the network interface comprising circuitry to;
signal to the at least one processor after receipt of packet data; and
initiate storage in the at least one cache of the at least one processor of at least a portion of the packet data, wherein the storage of the at least a portion of the packet data is not solicited by the processor;
instructions disposed on an article of manufacture, the instructions to cause the at least one processor to provide multiple threads of execution to process packets received by the network interface controller, individual threads including instructions to;
yield execution by the at least one processor at multiple points within the thread'"'"'s flow of execution to a different one of the threads;
fetch data into the at one least one cache of the at least one processor before subsequent instructions access the fetched data;
initiate, by the circuitry to independently copy data, a copy of at least a portion of a packet received by the network interface controller from a first set of locations in the randomly accessible memory to a second set of locations in the at least one randomly accessible memory.
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Abstract
In general, the disclosure describes a variety of techniques that can enhance packet processing operations.
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Citations
31 Claims
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1. A system, comprising:
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at least one processor including at least one respective cache;
at least one interface to at least one randomly accessible memory; and
circuitry to, in response to a processor request, independently copy data from a first set of locations in the randomly accessible memory to a second set of locations in the randomly accessible memory;
at least one network interface, the network interface comprising circuitry to;
signal to the at least one processor after receipt of packet data; and
initiate storage in the at least one cache of the at least one processor of at least a portion of the packet data, wherein the storage of the at least a portion of the packet data is not solicited by the processor;
instructions disposed on an article of manufacture, the instructions to cause the at least one processor to provide multiple threads of execution to process packets received by the network interface controller, individual threads including instructions to;
yield execution by the at least one processor at multiple points within the thread'"'"'s flow of execution to a different one of the threads;
fetch data into the at one least one cache of the at least one processor before subsequent instructions access the fetched data;
initiate, by the circuitry to independently copy data, a copy of at least a portion of a packet received by the network interface controller from a first set of locations in the randomly accessible memory to a second set of locations in the at least one randomly accessible memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system, comprising:
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at least one interface to at least one processor having at least one cache;
at least one interface to at least one randomly accessible memory;
at least one network interface;
circuitry to independently copy data from a first set of locations in a randomly accessible memory to a second set of locations in a randomly accessible memory in response to a command received from the at least one processor; and
circuitry to place data received from the at least one network interface in the at least one cache of the at least one processor. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. An article of manufacture comprising instructions that when executed cause a processor to perform operations comprising:
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receiving at a processor an indication of receipt of one or more packets; and
if more than one packet was received, fetching at least the headers of multiple ones of the more than one packet into a cache of the processor before instructions executed by the processor operate on all of the headers of the multiples ones of the more than one packet. - View Dependent Claims (22, 23, 25, 26)
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24. An article of manufacture comprising instructions that when executed cause a processor to perform operations comprising:
providing multiple threads of execution of at least one set of instructions, at least one of the set of instructions comprising;
multiple yields of execution to a different one of the multiple threads;
multiple fetches to load data into a processor cache, the data fetched comprising data selected from the following group;
(1) a reference to a Transmission Control Block (TCB) of a Transmission Control Protocol/Internet Protocol (TCP/IP) packet;
(2) a TCB of a TCP/IP packet; and
(3) a header of a TCP/IP packet.
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27. A method comprising:
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at a network interface controller;
receiving at least one link layer frame, the link layer frame encapsulating at least one Transmission Control Protocol/Internet Protocol packet;
determining a checksum for the at least one encapsulated Transmission Control Protocol/Internet Protocol packet;
determining a hash based on, at least, a source Internet Protocol address, a destination Internet Protocol address, a source port, and a destination port identified by an Internet Protocol header and a Transmission Control Protocol header of the Transmission Control Protocol/Internet Protocol packet;
signaling an interrupt to at least one processor after receipt of at least a portion of the at least one link layer frame;
initiating placement of, at least, the Internet Protocol header and the Transmission Control Protocol header into a cache of the at least one processor prior to a processor request to access a memory address identifying storage of the Internet Protocol header and the Transmission Control Protocol header;
at circuitry interconnecting the processor, the network interface controller, and at least one randomly accessible memory;
receiving a request from the processor to independently transfer at least a portion of a payload of a Transmission Control Protocol segment from a first set of memory locations in a randomly accessible memory to a second set of memory locations in the at least one randomly accessible memory;
at the processor;
providing multiple threads of execution, wherein individual ones of the multiple threads execute a set of instructions to perform operations that include;
at least one yield of execution to a different one of the multiple threads; and
at least one fetch to load data into a processor cache, the data fetched selected from the following group;
(1) a reference to Transmission Control Blocks (TCBs) of the a Transmission Control Protocol/Internet Protocol (TCP/IP) packet;
(2) the TCB of a TCP/IP packet; and
(3) a header of a TCP/IP packet - View Dependent Claims (28, 29)
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30. A system comprising:
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a network interface, the network interface comprising circuitry to;
receive at least one link layer frame, the link layer frame encapsulating at least one Transmission Control Protocol/Internet Protocol packet;
determine a checksum for the Transmission Control Protocol/Internet Protocol packet;
determine a hash based on, at least, a source Internet Protocol address, a destination Internet Protocol address, a source port, and a destination port identified by an Internet Protocol header and a Transmission Control Protocol header of the Transmission Control Protocol/Internet Protocol packet;
signal to at least one processor after receipt of at least a portion of the at least one link layer frame;
initiate placement of, at least, the Internet Protocol header and the Transmission Control Protocol header into a cache of the at least one processor prior to a processor request to access a memory address identifying storage of the Internet Protocol header and the Transmission Control Protocol header;
circuitry interconnecting the processor, the network interface, and at least one randomly accessible memory, the circuitry comprising circuitry to;
receive a request from the processor to independently transfer at least a portion of a payload of a Transmission Control Protocol segment from a first set of memory locations in a randomly accessible memory to a second set of memory locations in the at least one randomly accessible memory;
the processor including the at least one cache; and
an article of manufacture comprising instructions that when executed cause a processor to perform operations comprising;
providing multiple threads of execution, wherein individual ones of the multiple threads execute a set of instructions to perform operations that include;
multiple yields of execution to a different one of the multiple threads; and
multiple fetches to load data into a processor cache, the data fetched selected from the following group;
(1) a reference to Transmission Control Blocks (TCBs) of the a Transmission Control Protocol/Internet Protocol (TCP/IP) packet;
(2) the TCB of a TCP/IP packet; and
a header of a TCP/IP packet - View Dependent Claims (31)
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Specification