Semiconductor device and manufacturing method thereof

• US 20060073647A1
• Filed: 12/07/2004
• Published: 04/06/2006
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Inaba, Satoshi
• Granted Patent: US 7,456,472 B2
• Time in Patent Office: Days
• US Class Current: 438/157
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprising a multi Fin-FET structure capable of suppressing short channel effects, controlling a threshold voltage, driving a high current, and operating in a high-speed comprises a source region and a drain region disposed on a semiconductor substrate, a plurality of fins interconnecting the source region and drain region, a first gate electrode disposed on the semiconductor substrate and to one side face of each fin, a second gate electrode disposed on the semiconductor substrate and to the other side face of the fin to face the first gate electrode, and separated from the first gate electrode, a plurality of first pad electrodes connected to respective first gate electrode, a first wiring interconnecting the plurality of first pad electrodes, a plurality of second pad electrodes connected to respective second gate electrode, and a second wiring interconnecting the plurality of second pad electrodes.

Claims

1. A semiconductor device comprising:

a source region and a drain region disposed on a semiconductor substrate;

a plurality of fins which interconnect the source region and the drain region;

a first gate electrode disposed on the semiconductor substrate and to one side face of each fin;

a second gate electrode disposed on the semiconductor substrate and to the other side face of the fin to face the first gate electrode with respect to the fin, and separated from the first gate electrode;

a plurality of first pad electrodes connected to respective first gate electrode;

a first wiring which interconnects the plurality of first pad electrodes;

a plurality of second pad electrodes connected to respective second gate electrode; and

a second wiring which interconnects the plurality of second pad electrodes.

2. The semiconductor device according to claim 1, wherein potentials of the first and second gate electrodes are independently controlled.

3. The semiconductor device according to claim 1, further comprising a stretched region stretched from the source region or the drain region toward the first or second gate electrode, and formed to be connected to an adjacent fin.

4. The semiconductor device according to claim 3, wherein the stretched region from the source region and the stretched region from the drain region are alternately arranged.

5. The semiconductor device according to claim 3, wherein the stretched region is formed only from the source region.

6. The semiconductor device according to claim 3, wherein the first and second pad electrodes are arranged not to overlap with the stretched region.

7. The semiconductor device according to claim 2, further comprising a stretched region stretched from the source region or the drain region toward the first or second gate electrode, and formed to be connected to an adjacent fin.

8. The semiconductor device according to claim 7, wherein the stretched region from the source region and the stretched region from the drain region are alternately arranged.

9. The semiconductor device according to claim 7, wherein the stretched region is formed only from the source region.

10. The semiconductor device according to claim 7, wherein the first and second pad electrodes are arranged not to overlap with the stretched region.

11. The semiconductor device according to claim 1, wherein a channel is formed only in one side face of the fin.

12. The semiconductor device according to claim 1, wherein the first and second gate electrodes are alternately arranged.

13. A semiconductor device comprising:

a source region and a drain region disposed on a semiconductor substrate;

a plurality of fins which interconnect the source region and the drain region;

a gate electrode disposed on the semiconductor substrate to cover each fin;

a stretched region stretched from the source region or the drain region toward the gate electrode, and formed to be connected to an adjacent fin;

a plurality of pad electrodes connected to the gate electrode; and

a wiring which interconnects the plurality of pad electrodes.

14. A method of manufacturing a semiconductor device, comprising:

forming an insulator on an active layer in a surface of a semiconductor substrate;

forming a pattern of an active region including a plurality of fins in the active layer and the insulator;

depositing a gate electrode material on the pattern of the active region;

forming pluralities of first and second gate electrodes to face a side face of the fin, in opposition to each other with respect to the fin and to be separated from each other by processing the gate electrode material;

introducing impurities of a first conductive type into the active region excluding a region thereof held between the first and second gate electrodes;

forming a plurality of first pad electrodes to be connected to the first gate electrodes;

forming a first wiring which interconnects the plurality of first pad electrodes;

forming a plurality of second pad electrodes to be connected to the second gate electrodes; and

forming a second wiring which interconnects the plurality of second pad electrodes.

15. The method according to claim 14, wherein the active region comprises a source region, a drain region, a channel region, and a stretched region stretched from the source region or the drain region toward the first or second gate electrode, and formed to be connected to an adjacent fin.

16. The method according to claim 15, wherein the stretched region from the source region and the stretched region from the drain region are alternately arranged.

17. The method according to claim 15, wherein the stretched region is formed only from the source region.

18. The method according to claim 14, wherein the first and second gate electrodes are alternately arranged.

19. A method of manufacturing a semiconductor device, comprising:

forming a first insulator on a semiconductor substrate;

forming a pattern of an active region including a plurality of fins in a surface region of the semiconductor substrate and the first insulator;

introducing impurities of a first conductive type into the surface of the semiconductor substrate;

depositing a second insulator on the semiconductor substrate to bury a lower portion of the fin;

depositing a gate electrode material on the pattern of the active region;

forming pluralities of first and second gate electrodes to face a side face of the fin, in opposition to each other with respect to the fin and to be separated from each other by processing the gate electrode material;

introducing impurities of a second conductive type into the active region excluding a region held between the first and second gate electrodes;

forming a plurality of first pad electrodes to be connected to the first gate electrode;

forming a first wiring which interconnects the plurality of first pad electrodes;

forming a plurality of second pad electrodes to be connected to the second gate electrode; and

forming a second wiring which interconnects the plurality of second pad electrodes.

20. A method of manufacturing a semiconductor device, comprising:

forming an insulator on an active layer disposed on a surface of a semiconductor substrate;

forming a pattern of an active region including a source region, a drain region, a plurality of fins, and a stretched region stretched from the source region or the drain region and formed to be connected to an adjacent fin in the active layer and the insulator;

depositing a gate electrode material on the pattern of the active region;

forming gate electrodes to face a side face of the fin, in opposition to each other with respect to the fin and being connected each other by processing the gate electrode material;

introducing impurities of a first conductive type into the active region excluding a region held between the gate electrodes;

forming a plurality of pad electrodes to be connected to the gate electrodes; and

forming a wiring which interconnects the plurality of pad electrodes.