Method for reduced N+ diffusion in strained Si on SiGe substrate

• US 20060073649A1
• Filed: 11/22/2005
• Published: 04/06/2006
• Est. Priority Date: 09/09/2003
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Dokumaci, Omer H.
• Granted Patent: US 7,297,601 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26566 of a cluster, e.g. using a gas cluster ion beam
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

Method for manufacturing a semiconductor device. The method includes forming source and drain extension regions in an upper surface of a SiGe-based substrate. The source and drain extension regions contain an N type impurity. Reducing vacancy concentration in the source and drain extension regions to decrease diffusion of the N type impurity contained in the first source and drain extension regions.

Claims

1. A method for manufacturing a semiconductor device, comprising forming, on source and drain extension regions in an upper surface of a SiGe-based substrate having an Si cap arranged over an SiGe layer, low vacancy regions which substantially overlap the source and drain regions by annihilating or trapping excessive vacancies, whereby a vacancy concentration and a diffusion of an N type impurity is reduced.

2. The method of claim 1, further comprising relaxing the SiGe layer.

3. The method of claim 2, further comprising straining biaxially in tension the Si cap layer to match an underlying relaxed SiGe lattice.

4. The method of claim 1, further comprising dividing the SiGe based substrate into an NMOS region and a PMOS region.

5. The method of claim 1, wherein the forming comprises providing an interstitial element or a vacancy-trapping element in the source and drain extension regions.

6. The method of claim 5, wherein the interstitial element is Si or O, and the vacancy-trapping element is F, N, Xe, Ar, He, Kr or a noble gas element.

7. The method of claim 1, wherein the forming comprises ion-implanting the interstitial element or the vacancy-trapping element onto the SiGe-based substrate.

8. The method of claim 7, wherein the step of ion-implanting the interstitial element or the vacancy trapping element comprises a step of ion-implanting the interstitial element or the vacancy trapping element at an implantation concentration of approximately 1×

10¹⁴ atoms/cm² to 1×

10¹⁶ atoms/cm² and at an implantation energy of approximately 0.3 KeV to 100 KeV.

9. The method of claim 8, wherein a concentration peak of the interstitial element or the vacancy-trapping element and a concentration peak of the N type impurity in the source and drain extension regions are formed at substantially the same depth from an upper surface of the Si cap layer.

10. The method of claim 9, wherein the concentration peak of the interstitial element or the vacancy-trapping element is formed at a depth of approximately 10 Å

to 20000 Å

from the upper surface of the Si cap layer.

11. The method of claim 1, further comprising a step of annealing.

12. The method of claim 11, wherein the step of annealing is performed at a temperature of approximately 700°

C. to 1200°

C. for approximately 1 second to 3 minutes.

13. The method of claim 1, further comprising a step of forming a gate electrode on the upper surface of the SiGe-based substrate with a gate oxide film therebetween.

14. The method of claim 1, further comprising a step of providing an interstitial element or a vacancy-trapping element in the source and drain regions.

15. The method of claim 14, wherein the interstitial element is Si or O, and the vacancy-trapping element is F, N, Xe, Ar, He, Kr or a noble gas element.

16. The method of claim 1, wherein the forming comprises a step of ion-implanting the interstitial element or the vacancy-trapping element.

17. The method of claim 1, wherein the forming comprises one of:

ensuring that an implant profile of an interstitial element or a vacancy-trapping element fully contains an N type impurity profile; and

ensuring that a concentration peak of the interstitial element element or the vacancy-trapping element is near an N type impurity peak so as to maximize a diffusion retardation.

18. A method for manufacturing a semiconductor device, comprising steps of:

forming low vacancy regions in an upper surface of an SiGe based substrate by annihilating or trapping excessive vacancies, whereby a vacancy concentration and a diffusion of an N type impurity is reduced; and

forming source and drain extension regions in the upper surface of the SiGe based substrate, the source and drain extension regions containing an N type impurity.

19. The method of claim 18, further comprising reducing vacancy concentration by providing an interstitial element or a vacancy-trapping element in the source and drain extension regions and wherein the interstitial element is Si or O, and the vacancy-trapping element is F, N, Xe, Ar, He, Kr or a noble gas element.

20. The method of claim 19, wherein the step of providing the interstitial element or vacancy-trapping element comprises a step of ion-implanting the interstitial element or the vacancy-trapping element onto the SiGe based substrate.