Software state replay

• US 20060074622A1
• Filed: 07/12/2005
• Published: 04/06/2006
• Est. Priority Date: 07/12/2004
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Reblewski, Frederic, Scott, David C., Marantz, Joshua D., Selvidge, Charles W.
• Granted Patent: US 7,480,610 B2
• Time in Patent Office: Days
• US Class Current: 703/23
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3692 for test results analysis
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for the specified partition at each clock cycle and the state values for the specified partition at intervals. Using the state and input values with a software model of the specified circuit design partition, the tool calculates the state values for the partition at every clock cycle. The software model may correspond to the partitioning information used to implement the circuit design across multiple configurable logic element devices, such as FPGAs. Thus, each software model may correspond to the portion of a circuit design emulated on a discrete FPGA integrated circuit.

Claims

1. A method of analyzing a partition of a circuit design, comprising:

sampling an emulator to obtain one or more input values provided at a first time to a partition of a circuit design being emulated;

sampling the emulator to obtain one or more first state values produced by the circuit design partition at the first time;

using the obtained one or more input values and the one or more first state values to execute a software model that describes the operation of the circuit design partition, so as to calculate one or more second state values produced by the circuit design partition at a second time; and

registering the one or more second state values in a tangible medium.

2. The method recited in claim 1, further comprising:

sampling the emulator obtain each input value provided at the second time to the circuit design partition being emulated; and

using each input value provided to the circuit design partition at the second time and the calculated one or more second state values to execute the software model, so as to calculate one or more third state values produced by the circuit design partition at a third time.

3. The method recited in claim 1, wherein

the circuit design is being emulated by a plurality of configurable logic devices;

and

the circuit design partition is a portion of the circuit design being emulated by a single one of the plurality of configurable logic devices.

4. The method recited in claim 3, wherein the configurable logic devices are field programmable gate arrays.

5. The method recited in claim 1, further comprising:

receiving synthesis information describing the circuit design partition from the emulator; and

creating the software model from the synthesis information.

6. The method recited in claim 1, wherein

the circuit design partition includes a plurality of time domains;

and

the software model includes a portion describing the operation of each time domain.

7. The method recited in claim 6, further comprising:

sampling an emulator to obtain

one or more cross-domain input values provided to the circuit design partition at one or more times prior to the first time, and

a time of arrival of each sampled cross-domain input; and

using the obtained one or more input values, the one or more first state values, and the one or more cross-domain input values and the time of arrival of each sampled cross-domain input to execute a software model that describes the operation of the circuit design partition, so as to calculate one or more second state values produced by the circuit design partition at a second time

8. The method recited in claim 1, further comprising:

providing each obtained input value and the one or more first state values to a remote computing resource for executing the software model; and

receiving the calculated one or more second state values from the remote computing resource.

9. The method recited in claim 1, wherein registering the one or more second state values in the tangible medium includes rendering the one or more second state values on a display.

10. The method recited in claim 1, wherein registering the one or more second state values in the tangible medium includes storing the one or more second state values in a memory medium.

11. A computer readable medium having computer-executable instructions for performing the method recited in claim 1.

12. A method recited of analyzing a circuit design partition, comprising

sampling an emulator emulating a partition of a circuit design to obtain

each cycle of a clock signal being provided to the emulated circuit design partition during a defined analysis period,

each input value provided to the emulated circuit design partition at every cycle during the defined analysis period, and

one or more state values produced by the emulated circuit design partition at specified state value sample times over the defined analysis period;

using the obtained input values, clock cycles and one or more sampled state values to execute a software model that describes the operation of the circuit design partition, so as to calculate state values produced by the circuit design partition during intervals between the specified state value sample times over the defined analysis period; and

registering at least the calculated state values in a tangible medium.

13. The method recited in claim 12, wherein

the circuit design is being emulated by a plurality of configurable logic devices;

and

the circuit design partition is a portion of the circuit design being emulated by a single one of the plurality of configurable logic devices.

14. The method recited in claim 13, wherein the configurable logic devices are field programmable gate arrays.

15. The method recited in claim 12, further comprising:

receiving synthesis information describing the circuit design partition from the emulator; and

creating the software model from the synthesis information.

16. The method recited in claim 12, wherein

the circuit design partition includes a plurality of time domains;

and

the software model includes a portion describing the operation of each time domain.

17. The method recited in claim 12, wherein registering the one or more calculated state values in the tangible medium includes rendering the one or more calculated state values on a display.

18. The method recited in claim 12, wherein registering the one or more calculated state values in the tangible medium includes storing the one or more calculated state values in a memory medium.

19. The method recited in claim 12, further comprising:

sampling the emulator emulating a second partition of the circuit design to obtain

each cycle of a second clock signal being provided to the emulated second circuit design partition during the defined analysis period,

each input value provided to the emulated second circuit design partition at every cycle of the second clock period during the defined analysis period, and

one or more second state values produced by the emulated second circuit design partition at second specified state value sample times over the defined analysis period;

using the obtained input values provided to the emulated second circuit design partition, the cycles of the second clock signal and the one or more sampled second state values to execute a second software model that describes the operation of the second circuit design partition, so as to calculate second state values produced by the second circuit design partition during intervals between the second specified state value sample times over the defined analysis period; and

registering at least the calculated second state values in a tangible medium.

20. The method recited in claim 19, further comprising:

providing each cycle of the first clock signal, each input value provided to the emulated first circuit design partition at every cycle of the first clock signal, and the sampled first state values to a first remote computing resource for executing the first software model;

receiving the calculated first state values from the first remote computing resource;

providing each cycle of the second clock signal, each input value provided to the emulated second circuit design partition at every cycle of the second clock signal, and the sampled second state values to a second remote computing resource for executing the second software model; and

receiving the calculated second state values from the second remote computing resource.

21. The method recited in claim 20, wherein the first remote processing computer resource executes the first software model in parallel with the second remote processing computer resource executing the second software model.

22. A computer readable medium having computer-executable instructions for performing the method recited in claim 12.

23. A software state replay tool, comprising:

a model creation module that creates a software model describing the operation of a partition of a circuit design; and

a data sampling module that provides a software model created by the model creation module with data sampled from the emulation of the circuit design partition.

24. The software state replay tool recited in claim 23, further comprising an emulator that emulates the circuit design partition.

25. The software state replay tool recited in claim 23, further comprising a data output interface tool that outputs state information produced by executing the software model.