Sensor-network processors using event-driven architecture

• US 20060075210A1
• Filed: 05/06/2005
• Published: 04/06/2006
• Est. Priority Date: 05/06/2004
• Status: Active Grant

• Current Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Original Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Inventors: Manohar, Rajit, Kelly, Clint
• Granted Patent: US 7,788,332 B2
• Time in Patent Office: Days
• US Class Current: 712/36
• CPC Class Codes: G01D 21/00 Measuring or testing not otherwise provided for
• CPC Class Codes: H04W 24/00 Supervisory, monitoring or testing arrangements
• CPC Class Codes: H04W 52/0216 using a pre-established activity schedule, e.g. traffic indication frame
• CPC Class Codes: H04W 52/0219 where the power saving management affects multiple terminals
• CPC Class Codes: H04W 80/00 Wireless network protocols or protocol adaptations to wireless operation
• CPC Class Codes: H04W 84/18 Self-organising networks, e.g. ad-hoc networks or sensor networks

Abstract

Event-driven processor architectures are particularly suited for use in multiple sensor node networks and simulators of such networks. A first variation of the processor is particularly suited for use in a sensor node in a wireless sensor network. Through use of the event-driven architecture and special message and timing coprocessors, this embodiment of the invention is optimized for low energy requirements and data monitoring operations in sensor networks. A second embodiment of the invention includes modifications necessary for use of the processor in a network simulation protocol.

Claims

1. A method for managing events in a processing system comprising the steps of:

receiving messages to be executed by a processor and placing each of said messages in a queue for access by said processor;

generating timing messages with said processor and placing said timing messages also in said queue for processing by said processor; and

executing said messages in said queue with said processor.