Thin film transistor array panel and method for manufacturing the same
First Claim
1. A thin film transistor array panel comprising:
- an insulating substrate;
a gate line formed on the insulating substrate and comprising a gate electrode;
a gate insulating layer formed on the gate line;
a semiconductor layer formed on the gate insulating layer and overlapping the gate electrode;
diffusion barriers formed on the semiconductor layer and containing nitrogen;
a data line crossing the gate line and comprising a source electrode partially contacting the diffusion barriers;
a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and
a pixel electrode electrically connected to the drain electrode.
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Accused Products
Abstract
The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode at on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
42 Citations
17 Claims
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1. A thin film transistor array panel comprising:
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an insulating substrate;
a gate line formed on the insulating substrate and comprising a gate electrode;
a gate insulating layer formed on the gate line;
a semiconductor layer formed on the gate insulating layer and overlapping the gate electrode;
diffusion barriers formed on the semiconductor layer and containing nitrogen;
a data line crossing the gate line and comprising a source electrode partially contacting the diffusion barriers;
a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and
a pixel electrode electrically connected to the drain electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A manufacturing method of a thin film transistor array panel, comprising:
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forming a gate line on an insulating substrate;
depositing a gate insulating layer and a first a-Si layer in sequence;
depositing a second a-Si layer doped with a conductive impurity and including nitrogen on the first a-Si layer;
patterning the second a-Si layer and the first a-Si layer to form a pre-diffusion barrier and a semiconductor layer;
forming a data line and a drain electrode partially overlapping the pre-diffusion barrier;
etching the pre-diffusion barrier exposed between the data line and the drain electrode to form diffusion barriers; and
forming a pixel electrode electrically connected to the drain electrode. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification