Vertical field-effect transistor in source-down structure

• US 20060076615A1
• Filed: 09/22/2005
• Published: 04/13/2006
• Est. Priority Date: 09/22/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Tihanyi, Jeno
• Granted Patent: US 7,375,395 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

The invention relates to a vertical field-effect transistor in source-down structure, in which the active zones (10, 7, 11) are introduced from trenches (5, 8, 9) into a semiconductor body (1), a source electrode (18) being connected via the filling (6) of a body trench (5) to a highly doped substrate (2) via a conductive connection (15).

Claims

1-10. -10. (canceled)

11. A vertical field-effect transistor in source-down structure, comprising:

a semiconductor body comprising a semiconductor substrate of a first conduction type, and a semiconductor layer of a second conduction type, opposite to the first conduction type, the semiconductor layer disposed on the semiconductor substrate and forming a main surface of the semiconductor body;

at least one first trench extending from the main surface to the semiconductor substrate, the first trench at least partially surrounded by a zone of the first conduction type and filled with polycrystalline semiconductor material which is doped with a dopant of the first conduction type;

at least one second trench and at least one third trench, each extending from the main surface into the semiconductor layer without reaching the semiconductor substrate, the first trench disposed between the second trench and the third trench with respect to a first direction, each of the second and third trenches at least partially surrounded by respective zones of the second conduction type and filled with polycrystalline semiconductor material which is doped with a dopant of the second conduction type;

at least one fourth trench extending from the main surface into the semiconductor layer, the fourth trench having walls and a base lined with an insulating layer, the fourth trench filled with conductive material and, in the first direction, is located at a distance from the first trench, and in a second direction, substantially perpendicular to the first direction, is located at a distance from the second and third trenches;

a conductive connection between the polycrystalline semiconductor material of the second trench and the polycrystalline semiconductor material of the first trench;

a source electrode electrically connected to the semiconductor substrate;

a drain electrode electrically connected to the polycrystalline semiconductor material of the third trench; and

a gate electrode electrically connected to the conductive material of the fourth trench.

12. The vertical field-effect transistor according to claim 11, wherein the first conduction type is the p-conduction type.

13. The vertical field-effect transistor according to claim 11, wherein the first trench is completely surrounded by the zone of the first conduction type.

14. The vertical field-effect transistor according to claim 11, wherein the second trench is completely surrounded by one of the zones of the second conduction type.

15. The vertical field-effect transistor according to claim 11, wherein the polycrystalline semiconductor material in the first, second and third trenches comprises polycrystalline silicon.

16. The vertical field-effect transistor according to claim 11, wherein the insulating layer in the fourth trench is formed from at least one of the group consisting of silicon dioxide and silicon nitride.

17. The vertical field-effect transistor according to claim 11, wherein the conductive material in the fourth trench is doped polycrystalline silicon.

18. The vertical field-effect transistor according to claim 11, wherein the conductive material in the fourth trench is doped metallic material.

19. The vertical field-effect transistor according to claim 11, wherein the conductive connection is formed from doped polycrystalline silicon.

20. The vertical field-effect transistor according to claim 11, wherein the conductive connection is provided on the main surface.

21. The vertical field-effect transistor according to claim 11, wherein the fourth trench extends as far as the semiconductor substrate.

22. An arrangement for use in a field-effect transistor, comprising:

a semiconductor body comprising a semiconductor substrate and of a first conduction type and a semiconductor layer of a second conduction type, at least a part of the semiconductor substrate forming a source of the field-effect transistor, the semiconductor layer disposed on the semiconductor substrate and forming a main surface of the semiconductor body;

at least a first trench extending from the main surface to the semiconductor substrate, the first trench at least partially surrounded by a zone of the first conduction type and filled with polycrystalline semiconductor material which is doped with a dopant of the first conduction type;

at least a second trench and at least a third trench, each extending from the main surface into the semiconductor layer without reaching the semiconductor substrate, the first trench disposed between the second trench and the third trench with respect to a first direction, each of the second and third trenches at least partially surrounded by respective zones of the second conduction type and filled with polycrystalline semiconductor;

at least one fourth trench extending from the main surface into the semiconductor layer, the fourth trench having walls and a base lined with an insulating layer, the fourth trench filled with conductive material and, in the first direction, is located at a distance from the first trench, and in a second direction, substantially perpendicular to the first direction, is located at a distance from the second and third trenches;

a conductive connection between the polycrystalline semiconductor material of the second trench and the polycrystalline semiconductor material of the first trench.

23. The arrangement according to claim 22, wherein the first conduction type is the p-conduction type.

24. The arrangement according to claim 22, wherein the first trench is completely surrounded by the zone of the first conduction type.

25. The arrangement according to claim 22, wherein the second trench is completely surrounded by one of the zones of the second conduction type.

26. The arrangement according to claim 22, wherein the polycrystalline semiconductor material in the first, second and third trenches comprises polycrystalline silicon.

27. The arrangement according to claim 22, wherein the insulating layer in the fourth trench is formed from at least one of the group consisting of silicon dioxide and silicon nitride.

28. The arrangement according to claim 22, wherein the conductive material in the fourth trench is doped polycrystalline silicon.

29. The arrangement according to claim 22, wherein the conductive material in the fourth trench is doped metallic material.

30. The arrangement according to claim 22, wherein the conductive connection is formed from doped polycrystalline silicon.