MOS-gated transistor with reduced miller capacitance

• US 20060076617A1
• Filed: 10/08/2004
• Published: 04/13/2006
• Est. Priority Date: 10/08/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher Boguslaw, Shenoy, Praveen Muraleedharan
• Granted Patent: US 7,265,415 B2
• Time in Patent Office: Days
• US Class Current: 257/333
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

Claims

1. A trench MOS-gated transistor comprising:

a first region of a first conductivity type;

a well region of a second conductivity type forming a pn junction with the first region, the well region having a flat bottom portion and a portion extending deeper than the flat bottom portion;

a gate trench extending into the well region; and

channel regions in the well region along outer sidewalls of the gate trench, wherein a first bottom portion of the gate trench terminates within the first region and a second bottom portion of the gate trench terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

2. The trench MOS-gated transistor of claim 1 further comprising:

a substrate of the first conductivity type, wherein the first region is an epitaxial layer extending over the substrate.

3. The trench MOS-gated transistor of claim 1 further comprising:

source regions of the first conductivity type in the well region, the source regions flanking each side of the gate trench.

4. The trench MOS-gated transistor of claim 1 wherein the gate trench comprises a dielectric layer lining the sidewalls and bottom of the gate trench, and the gate trench is at least partially filled with polysilicon.

5. The trench MOS-gated transistor of claim 1 wherein at its deepest point in the first region, the deeper portion of the well region is about 0.2-0.4 μ

m deeper than the flat bottom portion of the well region.

6. The trench MOS-gated transistor of claim 1 further comprising a second region of the second conductivity type in the first region, a third bottom portion of the gate trench terminating within the second region, the second region being spaced from the well region to form a gap therebetween, wherein a current flows through the gap when the transistor is in an on state.

7. The trench MOS-gated transistor of claim 1 wherein at least one of the first region and the well region is from one of crystalline silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and silicon germanium (SiGe).

8. A trench MOS-gated transistor comprising:

a substrate;

an epitaxial layer of a first conductivity type extending over and in contact with the substrate;

a well region of a second conductivity type formed in an upper portion of the epitaxial layer, the well region having a flat bottom portion and a plurality of portions extending deeper than the flat bottom portion;

a plurality of gate trenches extending into the well region; and

source regions of the first conductivity type formed in an upper portion of the well region, the source regions flanking each side of the plurality of trenches so as to form channel regions in the well region along outer sidewalls of each of the plurality of gate trenches, each of the plurality of gate trenches having a first plurality of bottom portions which extend through the well region and terminate within the epitaxial layer and a second plurality of bottom portions each terminating within a corresponding one of the plurality of deeper portions of the well region such that when the transistor is in an on state the plurality of deeper portions of the well region prevent a current from flowing through those channel region portions located directly above the deeper portions of the well region.

9. The trench MOS-gated transistor of claim 8 wherein at their deepest point in the epitaxial layer, the plurality of deeper portions of the well region are about 0.2-0.41 μ

m deeper than the flat bottom portion of the well region.

10. The trench MOS-gated transistor of claim 8 further comprising a plurality of regions of the second conductivity type in the epitaxial layer, a third plurality of bottom portions of each gate trench terminating within a corresponding one of the plurality of regions of the second conductivity type, the plurality of regions of the second conductivity type being spaced from the well region to form a gap therebetween, wherein a current flows through the gap when the transistor is in an on state.

11. The trench MOS-gated transistor of claim 8 wherein each of the plurality of gate trenches comprises a dielectric layer lining the sidewalls and bottom of the gate trench, and each gate trench is at least partially filled with polysilicon.

12. The trench MOS-gated transistor of claim 8 wherein at least one of the substrate, the epitaxial layer, the well region, and the source regions is from one of crystalline silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and silicon germanium (SiGe).

13. A trench MOS-gated transistor comprising:

a substrate of silicon material;

a layer of silicon material of a first conductivity type over the substrate;

a well region of a second conductivity type formed in an upper portion of the layer of silicon material;

a gate trench extending into the well region;

a source region of the first conductivity type flanking each side of the gate trench so as to form channel regions in the well region along outer sidewalls of the gate trench, the gate trench being filled with a polysilicon material at least up to and partially overlapping with the source regions; and

a region of silicon material of the second conductivity type surrounding a bottom portion of the trench such that a gap is formed between the region of silicon material and the well region through which gap a current flows when the transistor is in an on state.

14. The trench MOS-gated transistor of claim 13 wherein the layer of silicon material is an epitaxial layer extending over the substrate.

15. The trench MOS-gated transistor of claim 13 wherein the region of silicon material has a thickness in the range of 0.1-0.3 μ

m.

16. The trench MOS-gated transistor of claim 13 wherein the trench gate is stripe shaped and the region of silicon material partially extends along a length of the striped trench gate.

17. The trench MOS-gated transistor of claim 13 wherein the trench gate is stripe shaped and the region of silicon material extends along an entire length of the striped trench gate.

18. The trench MOS-gated transistor of claim 17 wherein the region of silicon material is electrically connected to the well region.

19. The trench MOS-gated transistor of claim 13 wherein the region of silicon material electrically floats.

20. The trench MOS-gated transistor of claim 13 wherein the well region has a flat bottom portion and a portion extending deeper than the flat bottom portion such that portions of the gate trench terminate within the deeper portion of the well region.

21. A method of forming a trench MOS-gated transistor, the method comprising:

providing a first region of a first conductivity type;

forming a well region of a second conductivity type in an upper portion of the first region;

forming a trench extending through the well region and terminating within the first region, portions of the well region extending along the trench sidewalls forming channel regions; and

implanting dopants of the second conductivity type along predefined portions of the bottom of the trench to form a plurality of second regions extending deeper than a bottom surface of the well region, each of the plurality of second regions being contiguous with the well region such that when the transistor is in an on state the plurality of second regions prevent a current from flowing through those channel region portions located directly above the plurality of second regions.

22. The method of claim 21 wherein the first region is an epitaxial layer, the method further comprising:

forming the epitaxial layer over a substrate of the first conductivity type.

23. The method of claim 21 further comprising:

lining the trench sidewalls and bottom with dielectric layer;

at least partially filling the trench with polysilicon material; and

forming source regions of the first conductivity type in the well region, the source regions flanking each side of the gate trench.

24. The method of claim 21 wherein at least one of the first region, the well region, and the plurality of second regions is from one of crystalline silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and silicon germanium (SiGe).

25. A method of forming a trench MOS-gated transistor, the method comprising:

providing a silicon substrate;

forming a silicon epitaxial layer of a first conductivity type over the substrate;

forming a well region of a second conductivity type in an upper portion of the silicon epitaxial layer;

forming a trench extending through the well region and terminating within the epitaxial silicon layer;

implanting dopants of the second conductivity type along the bottom of the trench to form a region of the second conductivity type extending along a bottom portion of the trench such that a gap is formed between the silicon region and the well region through which gap a current flows when the transistor is in an on state;

forming source regions of the first conductivity type flanking each side of the trench, whereby potions of the well region extending along outer sidewalls of each of the plurality of gate trenches form channel regions; and

filling the trench with a polysilicon material at least up to and partially overlapping with the source regions.

26. The method of claim 25 further comprising:

forming source regions of the first conductivity type flanking each side of the trench; and

filling the trench with a polysilicon material at least up to and partially overlapping with the source regions.

27. The method of claim 25 wherein the silicon region has a thickness in the range of 0.1-0.3 μ

m.

28. A method of forming a trench MOS-gated transistor, the method comprising:

providing a first region of a first conductivity type;

performing a shallow implant of dopants of a second conductivity type into the first region;

performing a deep implant of dopant of the second conductivity type into the first region;

performing a temperature cycle after the deep and shallow implant steps to drive the respective implanted dopants deeper into the first region to thereby form a well region corresponding to the shallow implant and a second region corresponding to the deep implant, the deepest portion of the second region being deeper than a bottom surface of the well region; and

forming a trench having a first portion extending through the well region and terminating within the first region and a second portion extending through the well region and terminating within the second region.

29. The method of claim 28 wherein portions of the well region extending along sidewalls of the trench form channel regions, and wherein after the temperature cycle the second region is contiguous with the well region such that the second region prevents a current from flowing through those channel region portions located directly above the second region.

30. The method of claim 28 wherein after the temperature cycle the second region is spaced from the well region such that after the trench is formed the spacing between the second region and the well region forms a gap through which a current flows when the transistor is in an on state.

31. The method of claim 28 wherein the deep implant step is carried out using a masking layer.

32. The method of claim 28 wherein at least one of the first region, the well region, and the second region is from one of crystalline silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and silicon germanium (SiGe).

33. A method of forming a trench MOS-gated transistor, the method comprising:

providing a first region of a first conductivity type;

performing a shallow implant of dopants of a second conductivity type into the first region;

performing a temperature cycle to drive the implanted dopants deeper into the first region;

performing a second implant of dopants of the second conductivity type into the first region;

performing a temperature cycle to drive the implanted dopants from the second implant step deeper into the silicon region and to drive the dopants from the shallow implant step even deeper into the silicon to thereby form a well region corresponding to the second implant and a second region corresponding to the shallow implant, the deepest portion of the second region being deeper than a bottom surface of the well region; and

forming a trench having a first portion extending through the well region and terminating within the silicon region and a second portion extending through the well region and terminating within the second region

34. The method of claim 33 wherein portions of the well region extending along sidewalls of the trench form channel regions, and after the temperature cycle the second region is contiguous with the well region such that the second region prevents a current from flowing through those channel region portions located directly above the second region.

35. The method of claim 33 wherein after the temperature cycle the second region is spaced from the well region such that after the trench is formed the spacing between the second region and the well region forms a gap through which a current flows when the transistor is in an on state.

36. The method of claim 33 wherein at least one of the first region, the well region, and the second region is from one of crystalline silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and silicon germanium (SiGe).