INTEGRATED CIRCUIT WITH BULK AND SOI DEVICES CONNECTED WITH AN EPITAXIAL REGION

• US 20060076628A1
• Filed: 10/08/2004
• Published: 04/13/2006
• Est. Priority Date: 10/08/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Anderson, Brent A.
• Granted Patent: US 7,274,073 B2
• Time in Patent Office: Days
• US Class Current: 257/373
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits

Abstract

An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or different crystal orientations. The present integrated circuit is made by forming a substrate with SOI and bulk regions separated by an embedded sidewall spacer (made of dielectric). The sidewall spacer is etched, forming a trench that is subsequently filled with epitaxial material. After planarizing, the substrate has SOI and bulk regions with a continuous semiconductor surface. A butted P-N junction and silicide layer can provide electrical connection between the SOI and bulk regions.

Claims

1. A semiconductor integrated circuit, comprising:

a) a semiconductor-on-insulator (SOI) region with a buried dielectric layer;

b) a bulk semiconductor region adjacent to the SOI region;

c) a trench filled with epitaxial semiconductor material disposed between the SOI region and bulk region.

2. The semiconductor integrated circuit of claim 1 further comprising a buried sidewall spacer between the SOI region and bulk region, and disposed under the trench filled with epitaxial semiconductor material.

3. The semiconductor integrated circuit of claim 1 further comprising:

a) a first type doping in the bulk region;

b) a second type doping in the SOI region;

c) a butted P-N junction between the first-type doping and second type doping, wherein the butted junction is disposed in the SOI region, or in the filled trench.

4. The semiconductor integrated circuit of claim 3 wherein the first type doping extends into the SOI region.

5. The semiconductor integrated circuit of claim 3 wherein the trench filled with epitaxial semiconductor material has the first type doping.

6. The semiconductor integrated circuit of claim 3 further comprising a metal silicide layer disposed on the butted P-N junction.

7. The semiconductor integrated circuit of claim 6 wherein the metal silicide layer is disposed on a portion of the bulk region having the first type doping and on a portion of the SOI region having the second type doping.

8. The semiconductor integrated circuit of claim 1 wherein the SOI region and bulk region have different crystal orientations.

9. The semiconductor integrated circuit of claim 8 wherein the SOI region and bulk region are made of silicon, and wherein the SOI region has a {110} crystal orientation, and the bulk region has a {100} crystal orientation.

10. A semiconductor integrated circuit, comprising:

a) a semiconductor-on-insulator (SOI) region with a buried dielectric layer;

b) a bulk semiconductor region adjacent to the SOI region;

c) a P-N junction formed from a first type doping in the bulk region and a second type doping in the SOI region;

d) a metal silicide layer disposed on and electrically bridging the P-N junction.

11. The semiconductor integrated circuit of claim 10 wherein the P-N junction is disposed in the SOI region.

12. The semiconductor integrated circuit of claim 10 wherein the P-N junction is disposed at the trench filled with epitaxial semiconductor material.

13. The semiconductor integrated circuit of claim 10 further comprising a trench filled with epitaxial semiconductor material disposed between the SOI region and bulk region.

17. The method of claim 13 wherein the sidewall spacer is completely removed in step (b).

18. The method of claim 13 wherein the sidewall spacer is partially removed in step (b).

14. A method for forming a semiconductor integrated circuit with an SOI region and a bulk region, comprising the steps of:

a) forming a substrate with and SOI region and a bulk region separated by an embedded sidewall spacer;

b) etching the sidewall spacer to form an empty trench; and

c) epitaxially depositing semiconductor material in the trench.

15. The method of claim 14 further comprising the steps of:

d) planarizing the wafer after step (c); and

e) forming a first type doping in the bulk region, and a second type doping in the SOI region, wherein a P-N junction between the first type doping and the second type doping is disposed in the SOI region or in the trench.

16. The method of claim 15 further comprising the step of:

f) forming a metal silicide layer across the P-N junction after step (f).