Direct mapped repair cache systems and methods
First Claim
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1. A repair cache system comprising:
- a main memory comprising identified valid memory locations and identified faulty memory locations;
a repair component comprising repair registers associated with the faulty memory locations; and
a repair verification router comprising repair locations associated with the faulty memory locations, wherein the repair verification router routes read/write requests for faulty memory locations to the repair component and routes read/write requests for identified valid memory locations to the main memory.
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Abstract
The present invention facilitates memory devices and operation thereof by employing a repair cache system 600 to correct or repair identified faulty memory locations. The repair cache system 600 includes a repair verification router that compares a memory address 604 for a read/write request to a list or series of repair locations 608. On identifying a matching repair location, a repair register 616 located within a repair register bank 615 is coupled to a data bus 626. Otherwise, a memory location within the main memory 630 and addressed by the memory address 604 is coupled to the data bus 626.
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Citations
22 Claims
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1. A repair cache system comprising:
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a main memory comprising identified valid memory locations and identified faulty memory locations;
a repair component comprising repair registers associated with the faulty memory locations; and
a repair verification router comprising repair locations associated with the faulty memory locations, wherein the repair verification router routes read/write requests for faulty memory locations to the repair component and routes read/write requests for identified valid memory locations to the main memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A direct mapped repair cache system comprising:
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a repair verification component comprising a list of repair locations and a list or comparators;
a repair register bank comprising a list of repair registers;
a main memory comprising identified valid memory locations and identified faulty memory locations;
a data bus selectively coupled to the repair register bank and the main memory; and
wherein the repair verification component compares a memory address of a read/write request to the list of repair locations with the list of comparators to identify a match, couples a matching repair register of the repair register bank to the data bus on identifying a match, and couples the main memory to the data bus on not identifying a match. - View Dependent Claims (12, 13, 14)
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15. A method of operating a direct mapped repair cache comprising:
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receiving a request for read/write access to a memory address;
comparing the memory address to a list of repair locations to identify a matching and valid repair location;
on failure to identify a matching and valid repair location, providing read/write access to a memory location in main memory addressed by the memory address; and
on identifying a matching and valid repair location, preventing read/write access to main memory and providing read/write access to a repair register associated with the matching and valid repair location. - View Dependent Claims (16, 17, 18)
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19. A method of configuring a repair cache system comprising:
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providing a memory array comprising memory locations;
testing the memory array to identify faulty memory locations and identify valid memory locations; and
associating repair registers and repair locations to the identified faulty memory locations, wherein the repair registers are individually associated to the repair locations. - View Dependent Claims (20, 21, 22)
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Specification