Method to form a passivation layer

• US 20060079034A1
• Filed: 10/12/2004
• Published: 04/13/2006
• Est. Priority Date: 10/12/2004
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.), Oregon State University (Oregon University System)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.), Oregon State University (Oregon University System)
• Inventors: Hong, David, Hoffman, Randy, Chiang, Hai, Wager, John
• Granted Patent: US 7,382,421 B2
• Time in Patent Office: Days
• US Class Current: 438/151
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Embodiments of methods, apparatuses, devices, and/or systems for forming a passivation layer are described.

Claims

1. An apparatus, comprising:

at least one thin film transistor (TFT) having;

a substrate;

a channel layer disposed over at least a portion of the substrate, wherein said channel layer comprises a semiconductive oxide, and wherein said channel layer comprises at least a first surface and a substantially opposing second surface;

a gate dielectric layer disposed adjacent to said first surface of said channel layer;

a passivation layer disposed adjacent to said second surface of said channel layer, wherein said passivation layer comprises one or more wide-bandgap dielectric materials.

2. The apparatus of claim 1, and further comprising:

one or more gate electrodes formed over at least a portion of said substrate, wherein the gate electrode is electrically coupled to said gate dielectric layer; and

one or more drain and source electrodes formed over at least a portion of said substrate, wherein said drain and source electrodes are electrically coupled to said channel layer.

3. The apparatus of claim 2, wherein said TFT comprises a top gate TFT.

4. The apparatus of claim 2, wherein said TFT comprises a bottom gate TFT.

5. The apparatus of claim 1, wherein said at least one TFT comprises a plurality of thin film transistors, wherein at least a portion of said thin film transistors are coupled to form circuitry.

6. The apparatus of claim 5, wherein said circuitry substantially comprises at least a portion of a display device.

7. The apparatus of claim 6, wherein said at least a portion of a display device comprises a backplane of an Active Matrix Liquid Crystal Display (AMLCD) device.

8. The apparatus of claim 5, wherein said circuitry substantially comprises at least a portion of a smart package.

9. The apparatus of claim 1, wherein said channel layer comprises one or more of:

zinc oxide, cadmium oxide, indium oxide, gallium oxide, tin oxide, silver oxide, copper oxide, germanium oxide, lead oxide and/or antimony oxide.

10. The apparatus of claim 1, wherein said channel layer is substantially comprised of an oxide comprising two or more of:

zinc, cadmium, indium, gallium, tin, silver, copper, germanium, lead and/or antimony.

11. The apparatus of claim 1, wherein said gate dielectric layer comprises one or more of:

zirconium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, silicon oxide, aluminum oxide, hafnium oxide, barium zirconate titanate, barium strontium titanate, silicon nitride, and/or silicon oxynitride.

12. The apparatus of claim 1, wherein said passivation layer comprises one or more of:

SiO_x, SiN_x, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, AlO_x, GaO_x, SbO_x, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, MgF_x, CaO_x, CaF_x, BaO_x, BaF_x, SrO_x, SrF_x, and/or one or more types of spin-on glass.

13. The apparatus of claim 1, wherein said passivation layer substantially comprises at least a portion of an interlevel dielectric layer.

14. The apparatus of claim 1, wherein said substrate comprises one or more of:

glass, silicon, silicon dioxide, and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polycarbonates (PC), polyethylenenaphthalates (PEN), and/or acrylics.

15. A method, comprising:

forming one or more thin film components, wherein at least a portion of one or more thin film components substantially comprises a gate dielectric layer, a channel layer and a passivation layer, wherein said channel layer substantially comprises a semiconductive oxide, and is formed substantially between at least a portion of the gate dielectric layer and at least a portion of the passivation layer, wherein said passivation layer substantially comprises one or more wide-bandgap dielectric materials; and

forming at least one circuit from said one or more thin film components, wherein at least one circuit comprises at least a portion of an electronic device.

16. The method of claim 15, wherein said at least one circuit substantially comprises at least a portion of a display device.

17. The method of claim 16, wherein said at least a portion of a display device comprises a backplane of an Active Matrix Liquid Crystal Display (AMLCD) device.

18. The method of claim 15, wherein said at least one circuit substantially comprises at least a portion of a smart package.

19. The method of claim 15, wherein said channel layer substantially comprises one or more of:

zinc oxide, cadmium oxide, indium oxide, gallium oxide, tin oxide, silver oxide, copper oxide, germanium oxide, lead oxide and/or antimony oxide.

20. The method of claim 15, wherein said channel layer substantially comprises an oxide comprising two or more of:

zinc, cadmium, indium, gallium, tin, silver, copper, germanium, lead and/or antimony.

21. The method of claim 15, wherein said gate dielectric layer substantially comprises one or more of:

zirconium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, silicon oxide, aluminum oxide, hafnium oxide, barium zirconate titanate, barium strontium titanate, silicon nitride, and/or silicon oxynitride.

22. The method of claim 15, wherein said passivation layer substantially comprises one or more of:

SiO_x, SiN_x, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, AlO_x, GaO_x, SbO_x, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, MgF_x, CaO_x, CaF_x, BaO_x, BaF_x, SrO_x, SrF_x, and/or one or more types of spin-on glass.

23. A device formed substantially by a process comprising:

forming one or more thin film components, wherein at least a portion of one or more thin film components substantially comprises a gate dielectric layer, a channel layer and a passivation layer, wherein said channel layer substantially comprises a semiconductive oxide, and is formed substantially between at least a portion of the gate dielectric layer and at least a portion of the passivation layer, wherein said passivation layer substantially comprises one or more wide-bandgap dielectric materials; and

forming at least one circuit from said one or more thin film components, wherein at least one circuit comprises at least a portion of an electronic device.

24. The device of claim 23, wherein said device substantially comprises at least a portion of an electronic display device.

25. The device of claim 24, wherein said at least a portion of a display device comprises a backplane of an Active Matrix Liquid Crystal Display (AMLCD) device.

26. The device of claim 23, wherein said device substantially comprises at least a portion of a smart package.

27. The device of claim 23, wherein said channel layer substantially comprises one or more of:

zinc oxide, cadmium oxide, indium oxide, gallium oxide, tin oxide, silver oxide, copper oxide, germanium oxide, lead oxide and/or antimony oxide.

28. The device of claim 23, wherein said channel layer substantially comprises an oxide comprising two or more of:

zinc, cadmium, indium, gallium, tin, silver, copper, germanium, lead and/or antimony.

29. The device of claim 23, wherein said gate dielectric layer substantially comprises one or more of:

zirconium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, silicon oxide, aluminum oxide, hafnium oxide, barium zirconate titanate, barium strontium titanate, silicon nitride, and/or silicon oxynitride.

30. The device of claim 23, wherein said passivation layer substantially comprises one or more of:

SiO_x, SiN_x, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, AlO_x, GaO_x, SbO_x, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, MgF_x, CaO_x, CaF_x, BaO_x, BaF_x, SrO_x, SrF_x, and/or one or more types of spin-on glass.

31. A method, comprising:

a step for forming one or more thin film components, wherein at least a portion of one or more thin film components substantially comprises a gate dielectric layer, a channel layer and a passivation layer, wherein said channel layer substantially comprises a semiconductive oxide, and is formed substantially between at least a portion of the gate dielectric layer and at least a portion of the passivation layer, wherein said passivation layer substantially comprises one or more wide-bandgap dielectric materials; and

a step for forming at least one circuit from said one or more thin film components, wherein at least one circuit comprises at least a portion of an electronic device.

32. The method of claim 31, wherein said electronic device substantially comprises a display device.

33. The method of claim 32, wherein said display device comprises an Active Matrix Liquid Crystal Display (AMLCD) device.

34. The method of claim 31, wherein said at least one circuit substantially comprises at least a portion of a smart package.

35. The method of claim 31, wherein said channel layer substantially comprises one or more of:

zinc oxide, cadmium oxide, indium oxide, gallium oxide, tin oxide, silver oxide, copper oxide, germanium oxide, lead oxide and/or antimony oxide.

36. The method of claim 31, wherein said channel layer substantially comprises an oxide comprising two or more of:

zinc, cadmium, indium, gallium, tin, silver, copper, germanium, lead and/or antimony.

37. The method of claim 31, wherein said gate dielectric layer substantially comprises one or more of:

zirconium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, silicon oxide, aluminum oxide, hafnium oxide, barium zirconate titanate, barium strontium titanate, silicon nitride, and/or silicon oxynitride.

38. The method of claim 31, wherein said passivation layer substantially comprises one or more of:

SiO_x, SiN_x, SiO_xN_y, SiO_xC_y, SiO_xC_yH_x, SiO_xF_y, GeO_x, AlO_x, GaO_x, SbO_x, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, MgF_x, CaO_x, CaF_x, BaO_x, BaF_x, SrO_x, SrF_x, and/or one or more types of spin-on glass.

39. An apparatus, comprising:

means for forming a thin film transistor (TFT) having;

a substrate;

a channel layer disposed over at least a portion of the substrate, wherein said channel layer comprises a semiconductive oxide, and wherein said channel layer comprises at least a first surface and a substantially opposing second surface;

a gate dielectric layer disposed adjacent to said first surface of said channel layer;

means for passivating, wherein said means for passivating comprises a passivation layer disposed adjacent to said second surface of said channel layer, wherein said passivation layer comprises one or more wide-bandgap dielectric materials.

40. The apparatus of claim 39, and further comprising:

means for forming one or more gate electrodes over at least a portion of said substrate, wherein the gate electrode is electrically coupled to said gate dielectric layer; and

means for forming one or more drain and source electrodes over at least a portion of said substrate, wherein said drain and source electrodes are electrically coupled to said channel layer.

41. The apparatus of claim 40, wherein said TFT comprises a top gate TFT.

42. The apparatus of claim 40, wherein said TFT comprises a bottom gate TFT.

43. The apparatus of claim 40, wherein said apparatus comprises a plurality of thin film transistors, wherein at least a portion of said thin film transistors are coupled to form circuitry.

44. The apparatus of claim 40, wherein said circuitry substantially comprises at least a portion of a display device.

45. The apparatus of claim 44, wherein said at least a portion of a display device comprises a backplane of an Active Matrix Liquid Crystal Display (AMLCD) device.

46. The apparatus of claim 40, wherein said at least one circuit substantially comprises at least a portion of a smart package.

47. The apparatus of claim 40, wherein said channel layer substantially comprises one or more of:

zinc oxide, cadmium oxide, indium oxide, gallium oxide, tin oxide, silver oxide, copper oxide, germanium oxide, lead oxide and/or antimony oxide.

48. The apparatus of claim 40, wherein said channel layer substantially comprises an oxide comprising two or more of:

zinc, cadmium, indium, gallium, tin, silver, copper, germanium, lead and/or antimony.

49. The apparatus of claim 40, wherein said gate dielectric layer substantially comprises one or more of:

zirconium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, silicon oxide, aluminum oxide, hafnium oxide, barium zirconate titanate, barium strontium titanate, silicon nitride, and/or silicon oxynitride.

50. The apparatus of claim 40, wherein said means for passivating substantially comprises a layer of one or more of:

SiO_x, SiN_x, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, AlO_x, GaO_x, SbO_x, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, MgF_x, CaO_x, CaF_x, BaO_x, BaF_x, SrO_x, SrF_x, and/or one or more types of spin-on glass.

51. The apparatus of claim 40, wherein said means for passivating substantially comprises at least a portion of an interlevel dielectric layer.

52. The apparatus of claim 40, wherein said gate dielectric layer is formed on at least a portion of a substrate, and said substrate substantially comprises one or more of:

glass, silicon, silicon dioxide, and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polycarbonates (PC), polyethylenenaphthalates (PEN), and/or acrylics.