METHOD AND STRUCTURE FOR IMPROVING CMOS DEVICE RELIABILITY USING COMBINATIONS OF INSULATING MATERIALS

• US 20060079046A1
• Filed: 10/12/2004
• Published: 04/13/2006
• Est. Priority Date: 10/12/2004
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation, Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining, Lim, Eng Hua
• Application Number:
  US10/711,897
• Publication Number:
  US 20060079046A1
• Time in Patent Office: Days
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method for improving hot carrier effects in complementary metal oxide semiconductor (CMOS) devices includes forming a first configuration of insulating material over a first group of the CMOS devices, and forming a second configuration of insulating material over a second group of the CMOS devices. The first and said second configurations of insulating material are formed subsequent to a silicidation of the CMOS devices and prior to formation of a first interlevel (ILD) dielectric material over the CMOS devices.

Claims

1. A method for improving hot carrier effects in complementary metal oxide semiconductor (CMOS) devices, the method comprising:

forming a first configuration of insulating material over a first group of the CMOS devices, said first group of the CMOS devices comprising NFET devices; and

forming a second configuration of insulating material over a second group of the CMOS devices, said second group of the CMOS devices comprises PFET devices;

wherein said first and said second configuration of insulating material are formed subsequent to a silicidation of the CMOS devices and prior to formation of a first interlevel (ILD) dielectric material over the CMOS devices; and

wherein said first configuration of insulating material comprises a tensile layer over said NFET devices and said second configuration of insulating material comprises a compressive layer over said PFET devices.

2. The method of claim 1, wherein said first configuration of insulating material further comprises at least a pair of individual insulating layers, and said second configuration of insulating material further comprises a single insulating layer.

4. The method of claim 2, wherein said first group of the CMOS devices comprises gate oxide thicknesses of a first range and said second group of the CMOS devices comprises gate oxide thicknesses of a second range.

5. The method of claim 2, wherein said pair of individual insulating layers further comprises a first nitride layer and an oxide layer, and said single insulating layer further comprises a second nitride layer.

6. The method of claim 5, wherein said first nitride layer is a tensile nitride layer, and said second nitride layer is a compressive nitride layer.

7. The method of claim 6, wherein said first nitride layer is Si₃N₄ deposited using a BTBAS (Bis(TertiaryButylAmino)Silane) precursor, said second nitride layer is Si₃N₄ deposited by plasma enhanced chemical vapor deposition (PECVD) using a silane (SiH₂) precursor, and said oxide layer is tetraethyl orthosilicate (TEOS).

8. The method of claim 2, wherein said pair of individual insulating layers further comprises a first nitride layer and a third nitride layer, and said single insulating layer further comprises a second nitride layer.

9. The method of claim 2, wherein said pair or individual insulating layers further comprises a first nitride layer and an oxide layer, and said single insulating layer further comprises said first nitride layer.

10. The method of claim 2, wherein said pair of individual insulating layers further comprises a first nitride layer and a second nitride layer, and said single insulating layer further comprises said first nitride layer.

11. The method of claim 1, wherein:

said first configuration of insulating material further comprises one of a single nitride layer and a single oxide layer; and

said second configuration of insulating material further comprises one of a single nitride layer, a single oxide layer, and a combination of a nitride and an oxide layer.

12. The method of claim 1, wherein said first configuration of insulating material comprises a compressive material and said second configuration of insulating material comprises a tensile material.

22. The structure of claim 12, wherein said pair of individual insulating layers further comprises a first nitride layer and a second nitride layer, and said single insulating layer further comprises said first nitride layer.

3. (canceled)

13. A structure for improving hot carrier effects in complementary metal oxide semiconductor (CMOS) devices, comprising:

a first configuration of insulating material formed over a first group of the CMOS devices; and

a second configuration of insulating material formed over a second group of the CMOS devices;

wherein said first and said second configurations of insulating material are formal subsequent to a silicidation of the CMOS devices and prior to formation of a first interlevel (ILD) dielectric material over the CMOS devices.

14. The structure of claim 13, wherein said first configuration further comprises at least a pair of individual insulating layers, and said second configuration of insulating devices further comprises a single insulating layer.

15. The structure of claim 14, wherein said first group of the CMOS devices comprises NFET devices and said second group of the CMOS devices comprises PFET devices.

16. The structure of claim 14, wherein said first group of the CMOS devices comprises gate oxide thicknesses of a first range and said second group of the CMOS devices comprises gate oxide thicknesses of a second range.

17. The structure of claim 14, wherein said pair of individual insulating layers further comprises a first nitride layer and an oxide layer, and said single insulating layer further comprises a second nitride layer.

18. The structure of claim 17, wherein said first nitride layer is a tensile nitride layer, and said second nitride layer is a compressive nitride layer.

19. The structure of claim 18, wherein said first nitride layer is Si₃N₄ deposited using a BTBAS (Bis(TertiaryButylAmino)Silane) precursor, said second nitride layer is Si₃N₄ deposited by plasma enhanced chemical vapor deposition (PECVD) using a silane (SiH₂) precursor, and said oxide layer is tetracthyl orthosilicate (TEOS).

20. The method of claim 14, wherein said pair of individual insulating layers further comprises a first nitride layer and a third nitride layer, and said single insulating layer further comprises a second nitride layer.

21. The structure of claim 14, wherein said pair of individual insulating layers further comprises a first nitride layer and an oxide layer, and said single insulating layer further comprises said first nitride layer.

23. The method of claim 13, wherein:

said first configuration or insulating material further comprises one of a single nitride layer and a single oxide layer; and

said second configuration of insulating material further comprises one of a single nitride layer, a single oxide layer, and a combination of a nitride and an oxide layer.

24. The method of claim 13, wherein said first configuration of insulating material comprises a compressive material and said second configuration of insulating material comprises a tensile material.