METHOD OF MANUFACTURING OF THIN BASED SUBSTRATE

• US 20060079079A1
• Filed: 10/11/2004
• Published: 04/13/2006
• Est. Priority Date: 10/11/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Natekar, Devendra, Muthukumar, Sriram
• Granted Patent: US 7,049,208 B2
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.

Claims

1. A method, comprising:

forming a dielectric layer on a first side of a silicon layer;

forming conductive trace layer on the dielectric layer;

thinning the silicon layer after forming the conductive traces; and

forming vias through the thinned silicon layer, the vias being electrically connected to the traces.

2. The method of claim 1, further comprising:

forming a first plurality of conductive pads on the second side of the silicon layer, the conductive pads being electrically connected to the vias;

positioning the second side of the thinned silicon layer adjacent a microelectronic die with a plurality of electronic contacts; and

electrically and mechanically coupling the first plurality of conductive pads to the plurality of electronic contacts.

3. The method of claim 2, further comprising:

forming a second dielectric layer on the conductive trace layer;

forming a second plurality of conductive pads on the second dielectric layer, the second plurality of conductive pads being electrically connected to the vias by traces in the conductive trace layer;

positioning the second plurality of conductive pads adjacent a printed circuit board; and

electrically and mechanically coupling the second plurality of conductive pads to the printed circuit board.

4. The method of claim 3, wherein the first plurality of conductive pads has a first pitch and the second plurality of conductive pads having a second pitch larger than the first pitch.

5. The method of claim 1, further comprising forming a plurality of devices on the silicon layer.

6. A method, comprising:

forming a substrate, comprising;

forming a plurality of build up layers, including a plurality of conductive layers and a plurality of dielectric layers, on a first major surface of a base layer;

thinning the base layer after forming the build up layers;

forming holes through the thinned base layer; and

forming conductive vias in the holes, the conductive vias being electrically connected to the plurality of conductive layers;

positioning the substrate adjacent a microelectronic die;

coupling the substrate to the die; and

wherein the substrate and the die have substantially similar coefficients of thermal expansion.

7. The method of claim 6, wherein the base layer comprises silicon.

8. The method of claim 7, wherein, after the substrate is coupled to the die, a second major surface of the substrate opposite to the first major surface is positioned adjacent the die.

9. The method of claim 8, wherein at least portions of the second major surface comprises a surface of the silicon base layer.

10. A system, comprising:

a microelectronic die having a first plurality of electrical contacts with a first pitch and having a first coefficient of thermal expansion;

a substrate, having;

a first major surface adjacent to the microelectronic die;

a second major surface opposite the first major surface;

a second plurality of electrical contacts with a second pitch about the equal to the first pitch on the first major surface electrically connected to the first plurality of electrical contacts of the microelectronic die;

a base layer with a first side closer to the microelectronic die and a second side further from the microelectronic die;

a plurality of build up layers on the second side of the base layer, the build up layers including metal traces separated by dielectric layers;

a plurality of vias through the base layer to provide an electrical connection between the second plurality of electrical contacts and the metal traces; and

a third plurality of electrical contacts at a boundary of the plurality of build up layers farthest from the base layer, the third plurality of contacts being electrically connected to the plurality of vias by the metal traces and having a third pitch greater than the first and second pitches; and

a printed circuit board electrically connected to the third plurality of electrical contacts.

11. The system of claim 10, wherein the base layer comprises silicon.

12. The system of claim 10, wherein the second pitch is in a range from about 65 microns to about 200 microns.

13. The system of claim 10, wherein the second pitch is in a range from about 120 microns to about 180 microns.

14. The system of claim 10, wherein the base layer has a thickness less than about 150 microns.

15. The system of claim 10, wherein the vias have a diameter of about 12 microns, and the second pitch is in a range from about 65 microns to about 200 microns.

16. The system of claim 10, wherein the plurality of build up layers comprise more than five dielectric layers.

17. The system of claim 10, wherein each of the plurality of build up layers has a thickness less than about thirty microns.

18. The system of claim 10, wherein the printed circuit board comprises a printed wired board.

19. The system of claim 10, further comprising:

a graphics processor communicably connected to the die; and

mass storage communicably connected to the die.

20. A device, comprising:

a silicon layer with a first side and a second side opposite the first side;

a plurality of conductive vias through the silicon layer from the first side to the second side;

a first dielectric layer on the second side;

a first conductive trace layer having conductive traces on the first dielectric layer, the conductive traces being electrically connected to the conductive vias;

a second dielectric layer on the first conductive trace layer; and

a first plurality of conductive contacts, the plurality of conductive contacts being electrically connected to the conductive traces.

21. The device of claim 20, further comprising a plurality of active devices formed on the silicon layer.

22. The device of claim 20, further comprising a plurality of passive devices formed on the silicon layer.

23. The device of claim 20, further comprising third, fourth, and fifth sixth dielectric layers alternating with second, third, and fourth conductive trace layers on the second dielectric layers.

24. The device of claim 20, further comprising a second plurality of conductive contacts on the first side of the silicon layer, wherein the first plurality of conductive contacts has a first pitch and the second plurality of conductive contacts has a second pitch smaller than the first pitch, and the first plurality of conductive contacts are electrically connected to the second plurality of conductive contacts.

25. The device of claim 20, further comprising a microelectronic die having a third plurality of conductive contacts with a third pitch approximately the same as the second pitch, the microelectronic die positioned adjacent the first side of the silicon layer and wherein the second plurality of conductive contacts are electrically connected to the third plurality of conductive contacts.

26. The device of claim 20, further comprising a printed circuit board electrically and mechanically connected to the first plurality of conductive contacts.