Enhanced bus transactions for efficient support of a remote cache directory copy

• US 20060080511A1
• Filed: 10/08/2004
• Published: 04/13/2006
• Est. Priority Date: 10/08/2004
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kriegel, Jon K., Hoover, Russell D., Mejdrich, Eric O., Woodward, Sandra S.
• Application Number:
  US10/961,742
• Publication Number:
  US 20060080511A1
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)

Abstract

Methods and apparatus are provided that may be utilized to maintain a copy of a processor cache directory on a remote device that may access data residing in a cache of the processor. Enhanced bus transactions containing cache coherency information used to maintain the remote cache directory may be automatically generated when the processor allocates or de-allocates cache lines. Rather than query the processor cache directory prior to each memory access to determine if the processor cache contains an updated copy of requested data, the remote device may query its remote copy.

Claims

1. A method of maintaining coherency of data accessed by a remote device, comprising:

receiving, by a remote device, a bus transaction containing cache coherency information indicating a change to a cache directory residing on a processor that initiated the bus transaction; and

updating a cache directory residing on the remote device, based on the cache coherency information, to reflect the change to the cache directory residing on the processor.

2. The method of claim 1, wherein the updating the cache directory residing on the remote device comprises updating an entry corresponding to a cache line indicated by the cache coherency information.

3. The method of claim 2, wherein the cache coherency information comprises a set of bits indicative of a cache line within an associative set of cache lines.

4. The method of claim 3, further comprising determining the associative set of cache lines based on an address provided in the bus transaction.

5. The method of claim 2, wherein the cache coherency information comprises an indication of whether data stored in a cache line being replaced is to be written out to memory.

6. The method of claim 1, wherein the cache coherency information comprises a bit indicating at least one of:

whether a new cache line is being allocated or whether a cache line is being de-allocated.

7. A method of maintaining coherency of data, wherein the data is cacheable by a processor and accessible by a remote device, comprising:

maintaining a cache directory on the remote device, the cache directory containing entries indicating the contents and coherency state of corresponding cache lines on the processor as indicated by cache coherency information transmitted to the remote device by the processor;

receiving, at the remote device, a request to access data associated with a memory location;

examining the cache directory residing on the remote device to determine if a copy of the requested data resides in a processor cache in a non-invalid state; and

it the cache directory residing on the remote device indicates a copy of the requested data does not reside in a processor cache in a non-invalid state, accessing the requested data from memory without sending a request to the processor.

8. The method of claim 7, further comprising, if the cache directory residing on the remote device indicates a copy of the requested data does reside in a processor cache in a non-invalid state, sending a bus command to the processor to at least one of:

invalidate or cast out its copy of the requested data.

9. The method of claim 7, further comprising:

receiving, by the remote device, a bus transaction initiated by the processor containing cache coherency information indicating a change to a cache directory residing on the processor; and

updating the cache directory residing on the remote device, based on the cache coherency information, to reflect the change to the cache directory residing on the processor.

10. A method of maintaining coherency, comprising:

allocating a cache line by a processor, resulting in a change to a cache directory residing on the processor; and

generating a bus transaction to a remote device containing cache coherency information identifying the allocated cache line.

11. The method of claim 10, wherein generating the bus transaction comprises creating a data packet with one or more bits containing the cache coherency information.

12. The method of claim 10, wherein the bus transaction corresponds to a read of data to be stored in the allocated cache line.

14. The method of claim 10, wherein generating the bus transaction comprises creating a data packet with one or more bits containing the cache coherency information.

15. The method of claim 14, wherein the bus transaction corresponds to a cast out of data previously stored in the de-allocated cache line.

13. A method of maintaining cache coherency, comprising:

de-allocating a cache line by a processor, resulting in a change to a cache directory residing on the processor; and

generating a bus transaction to a remote device containing cache coherency information identifying the de-allocated cache line.

16. A device configured to access data stored in memory and cacheable by a processor, comprising:

one or more processing cores;

a cache directory indicative of contents of a cache residing on the processor; and

snoop logic configured to receive cache coherency information sent by the processor in bus transactions and update the cache directory based on the cache coherency information, to reflect changes to the contents of the cache residing on the processor.

17. The device of claim 16, wherein the snoop logic is configured to receive cache coherency information indicating a cache line that has been de-allocated by the processor and invalidate a corresponding entry in the cache directory.

18. The device of claim 16, wherein the snoop logic is further configured to:

receive, from the processing core, a request to access data associated with a memory location;

examine the cache directory to determine if a copy of the requested data resides in a processor cache in a non-invalid state; and

if the cache directory residing on the remote device indicates a copy of the requested data does not reside in a processor cache in a non-invalid state, route the request to a memory controller to access the requested data from memory without sending a request to the processor.

19. A processor, comprising:

one or more processing cores;

a cache for storing data accessed from external memory by the processing cores;

a cache directory with entries indicating which memory locations are stored in cache lines of the cache and corresponding coherency states thereof; and

control logic configured to detect internal bus transactions indicating the allocation and de-allocation of cache lines and, in response, generate external bus transactions to a remote device, each containing cache coherency information indicating cache line that has been allocated or de-allocated.

20. A coherent system, comprising:

a processor having a cache for storing data accessed from external memory, a cache directory with entries indicating which memory locations are stored in cache lines of the cache and corresponding coherency states thereof, and control logic configured to detect internal bus transactions indicating the allocation and de-allocation of cache lines and, in response, generate bus transactions, each containing cache coherency information indicating cache line that has been allocated or de-allocated; and

a remote device having a remote cache directory indicative of contents of the cache residing on the processor and snoop logic configured to update the remote cache directory, based on cache coherency information contained in the external bus transactions generated by the processor control logic, to reflect allocated and de-allocated cache lines of the processor cache.

21. The system of claim 20, wherein the remote device is a graphics processing unit (GPU) including one or more graphics processing cores.

22. The system of claim 21, wherein the snoop logic is configured to:

receive a memory access request issued by a graphics processing core;

determine if a copy of data targeted by the request is contained in the processor cache in a non-invalid state by examining the remote cache directory; and

if not, route the request to external memory without sending a request to the processor.

23. The system of claim 22, wherein the snoop logic is configured to route request to external memory via a memory controller integrated with the remote device.