ASICs having more features than generally usable at one time and methods of use
First Claim
1. A method for utilizing a mega-ASIC comprising the steps of:
- (a) providing an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads; and
(b) providing in the predefined circuit space, an excess of programmably activateable ASIC functional blocks, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuitry, which if provided, is provided for recovering from spot manufacturing defects, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks.
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Accused Products
Abstract
More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different market spaces (e.g., in different countries where different interoperability standards are chosen) and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. Customer behavior can be fickle. If market trends evolve towards demand for functionality #2 instead of an originally, more expected, functionality #1, the mass produced of the crammed chip (or chip set) is not out of necessarily out of luck. If the mass produced had enough foresight to cram in functionality #2 as well as functionality #1, the producer can programmably activate #2, and deactivate #1 as market demand suddenly shifts in a given market space. In one embodiment, a mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a mass produced can quickly respond to shifting market demands, thus addresses both time to market and product life issues. The invention allows a small chip designer to simultaneously address more than one market or customer space with one ASIC chip thereby reducing the design cost per product design. By selectively activating the excessive and selectable ASIC functionalities, the small ASIC chip designer can appear to sport different features for different customers and different markets at different times with just one chip, thus he can aggregate the demand of different customers and different markets to achieve economies of scale, and of inventory management and control.
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Citations
18 Claims
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1. A method for utilizing a mega-ASIC comprising the steps of:
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(a) providing an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads; and
(b) providing in the predefined circuit space, an excess of programmably activateable ASIC functional blocks, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuitry, which if provided, is provided for recovering from spot manufacturing defects, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks. - View Dependent Claims (2, 3)
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4. A mega-ASIC comprising:
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(a) an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads; and
(b) an excess of ASIC functional blocks provided in said predefined circuit space, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuits, which if provided, are provided for recovering from spot manufacturing defects, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of reducing probability that a mass produced ASIC will lack market-demanded features in a future time space and market space, the method comprising:
(a) cramming more ASIC functionality into a monolithic chip (or chip set) than can probably or definitely be operative at one time when the chip is inserted into a broader, operative circuit, where the excessive ASIC functionality is chosen to anticipate different market development probabilities in a host of different market spaces (e.g., in different countries where different interoperability standards are chosen).
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17. Manufactured instructing signals for instructing an instructable machine to carry out a mega-ASIC configuring method for configuring a mega-ASIC comprising:
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(0.1) an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads; and
(0.2) an excess of ASIC functional blocks provided in said predefined circuit space, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuits, which if provided, are provided for recovering from spot manufacturing defects, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks, said manufactured instructing signals comprising;
(a) first signals for designating a subset of said excess of ASIC functional blocks as being activated.
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18. A method for selectively programming a large plurality of mega-ASICs comprising:
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(a) blanket programming the large plurality of mega-ASICs with first configuration data; and
(b) selectively re-programming a smaller subset of the large plurality of mega-ASICs with different, second configuration data.
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Specification