Three-dimensional memory system-on-a-chip
First Claim
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1. A system-on-a-chip integrated circuit, comprising:
- an embedded processor (eP) block and an embedded memory (eM) block;
a three-dimension memory (3D-M) block stacked on top of at least a portion of said eM block, said 3D-M block comprising at least one 3D-M level, said 3D-M level comprising a plurality of address-selection lines and 3D-M cells.
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Abstract
The present invention provides a three-dimensional memory (3D-M) system-on-a-chip (SoC). It takes full advantage of the difference in the number of interconnect levels between the embedded processor (eP) and embedded memory (eM) in an SoC chip. The un-used interconnect space on top of the eM block is converted into 3D-M. This conversion incurs minimum additional cost, but with significant benefits: 3D-M can add a large storage capacity to the SoC chip and therefore the chip becomes more powerful.
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Citations
20 Claims
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1. A system-on-a-chip integrated circuit, comprising:
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an embedded processor (eP) block and an embedded memory (eM) block;
a three-dimension memory (3D-M) block stacked on top of at least a portion of said eM block, said 3D-M block comprising at least one 3D-M level, said 3D-M level comprising a plurality of address-selection lines and 3D-M cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit, comprising:
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a first interconnect level;
a second interconnect level above said first interconnect level;
at least two different types of interconnects located between said first and second interconnect levels. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification