Semiconductor device

• US 20060081919A1
• Filed: 01/28/2005
• Published: 04/20/2006
• Est. Priority Date: 10/20/2004
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Inoue, Tomoki, Sugiyama, Koichi, Ninomiya, Hideaki
• Application Number:
  US11/044,065
• Publication Number:
  US 20060081919A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device comprising: a first-conductivity-type base layer; a second-conductivity-type emitter layer formed on a first main surface of said first-conductivity-type base layer; a collector electrode formed in contact with a surface of said second-conductivity-type emitter layer; a second-conductivity-type base layer formed on a second main surface of said first-conductivity-type base layer; a plurality of trenches which extend through said second-conductivity-type base layer to reach a predetermined depth of said first-conductivity-type base layer, and has a longitudinal direction in one direction; a gate electrode formed in said trench via a gate insulating film; a first-conductivity-type emitter layer selectively formed in contact with side walls of said trench, in a surface portion of said second-conductivity-type base layer; an emitter electrode formed in contact with a surface of said second-conductivity-type base layer and a surface of said first-conductivity-type emitter layer; and a second-conductivity-type semiconductor layer selectively formed in a region along the longitudinal direction of said trench, near the surface of said first-conductivity-type emitter layer.

Claims

1. A semiconductor device comprising:

a first-conductivity-type base layer;

a second-conductivity-type emitter layer formed on a first main surface of said first-conductivity-type base layer;

a collector electrode formed in contact with a surface of said second-conductivity-type emitter layer;

a second-conductivity-type base layer formed on a second main surface of said first-conductivity-type base layer;

a plurality of trenches which extend through said second-conductivity-type base layer to reach a predetermined depth of said first-conductivity-type base layer, and has a longitudinal direction in one direction;

a gate electrode formed in said trench via a gate insulating film;

a first-conductivity-type emitter layer selectively formed in contact with side walls of said trench, in a surface portion of said second-conductivity-type base layer;

an emitter electrode formed in contact with a surface of said second-conductivity-type base layer and a surface of said first-conductivity-type emitter layer; and

a second-conductivity-type semiconductor layer selectively formed in a region along the longitudinal direction of said trench, near the surface of said first-conductivity-type emitter layer.

2. A device according to claim 1, further comprising a first-conductivity-type barrier layer formed between said first-conductivity-type base layer and first-conductivity-type emitter layer.

3. A device according to claim 1, wherein

first and second regions are formed as regions surrounded by said trenches,

said first region has said first-conductivity-type emitter layer selectively formed in contact with the side walls of said trench, in the surface portion of said second-conductivity-type base layer, and said second-conductivity-type semiconductor layer selectively formed in the region along the longitudinal direction of said trench, near the surface of the first-conductivity-type emitter layer, and

said second region has a second-conductivity-type dummy layer.

4. A device according to claim 1, wherein in a surface portion of a region surrounded by said trenches, said second-conductivity-type semiconductor layer is formed in a region except for a portion where said first-conductivity-type emitter layer is in contact with said emitter electrode.

5. A device according to claim 1, wherein

said first-conductivity-type emitter layer has, in a surface portion of a region surrounded by said trenches, a first emitter region formed along the longitudinal direction of said trench, and a second emitter region formed along a direction perpendicular to the longitudinal direction of said trench, and

said second-conductivity-type semiconductor layer is formed at least on an intersection of said first and second emitter regions, in the surface portion of the region surrounded by said trenches.

6. A device according to claim 5, further comprising a second-conductivity-type semiconductor layer formed between said first emitter region of said first-conductivity-type emitter layer and said second-conductivity-type base layer.

7. A device according to claim 1, wherein

said first-conductivity-type emitter layer has, in a surface portion of a region surrounded by said trenches, a first emitter region formed along the longitudinal direction of said trench, and a second emitter region formed along a direction perpendicular to the longitudinal direction of said trench, and

said second-conductivity-type semiconductor layer is formed on said first emitter region except for an intersection of said first and second emitter regions, in the surface portion of the region surrounded by said trenches.

8. A device according to claim 1, wherein

said first-conductivity-type emitter layer has, in a surface portion of a region surrounded by said trenches, a first emitter region formed along the longitudinal direction of said trench, and a second emitter region formed along a direction perpendicular to the longitudinal direction of said trench, and

said second-conductivity-type semiconductor layer is formed into a shape of a stripe in the direction perpendicular to the longitudinal direction of said trench, except for an intersection of said first and second emitter regions, in the surface portion of the region surrounded by said trenches.

9. A device according to claim 1, wherein

said first-conductivity-type emitter layer has, in a surface portion of a region surrounded by said trenches, a plurality of first emitter regions formed along the longitudinal direction of said trench, and a plurality of second emitter regions formed along a direction perpendicular to the longitudinal direction of said trench, one end portion of each of said first emitter regions being connected to one of said second emitter regions, and the other end portion of each of said first emitter regions being separated from said second emitter regions, and

said second-conductivity-type semiconductor layer is formed on said first emitter region except for an intersection of said first and second emitter regions, in the surface portion of the region surrounded by said trenches.

10. A device according to claim 1, wherein

said first-conductivity-type emitter layer has, in a surface portion of a region surrounded by said trenches, a plurality of first emitter regions formed along the longitudinal direction of said trench, and a plurality of second emitter regions formed along a direction perpendicular to the longitudinal direction of said trench, a substantially central portion of each of said first emitter regions being connected to one of said second emitter regions, and two end portions of each of said first emitter regions being separated from other first emitter regions and said second emitter regions, and

said second-conductivity-type semiconductor layer is formed on said first emitter region except for an intersection of said first and second emitter regions, in the surface portion of the region surrounded by said trenches.

11. A semiconductor device comprising:

a first-conductivity-type base layer;

a second-conductivity-type emitter layer formed on a first main surface of said first-conductivity-type base layer;

a collector electrode formed in contact with a surface of said second-conductivity-type emitter layer;

a second-conductivity-type base layer formed on a second main surface of said first-conductivity-type base layer;

a plurality of trenches which extend through said second-conductivity-type base layer to reach a predetermined depth of said first-conductivity-type base layer;

a gate electrode formed in said trench via a gate insulating film;

a first-conductivity-type emitter layer selectively formed in contact with side walls of said trench, in a surface portion of said second-conductivity-type base layer;

an emitter electrode formed in contact with a surface of said second-conductivity-type base layer and a surface of said first-conductivity-type emitter layer; and

a second-conductivity-type semiconductor layer selectively formed in a region along a longitudinal direction of said trench, near the surface of said first-conductivity-type emitter layer,

wherein said trenches are formed into a mesh-like shape, and said gate electrode is formed into a mesh-like shape in said trench via said gate insulating film, and

in each region surrounded by said trenches,

said first-conductivity-type emitter layer is selectively formed along the side walls of said trench, in the surface portion of said second-conductivity-type base layer,

said emitter electrode is formed in contact with the surface of said second-conductivity-type base layer and the surface of said first-conductivity-type emitter layer, and

said second-conductivity-type semiconductor layer is selectively formed along the side walls of said trench, near the surface of said first-conductivity-type emitter layer.

12. A device according to claim 11, wherein in each region surrounded by said trenches,

said first-conductivity-type emitter layer is selectively formed along the side walls of said trench, in the surface portion of said second-conductivity-type base layer except for four corners,

said emitter electrode is formed in contact with the surface of said second-conductivity-type base layer and the surface of said first-conductivity-type emitter layer, and

said second-conductivity-type semiconductor layer is selectively formed along the side walls of said trench, near the surface of said first-conductivity-type emitter layer.

13. A device according to claim 11, wherein in each region surrounded by said trenches,

said emitter electrode is formed in contact with the surface of said second-conductivity-type base layer and the surface of said first-conductivity-type emitter layer, and

said second-conductivity-type semiconductor layer is selectively formed along the side walls of said trench, without being in contact with said emitter electrode, near the surface of said first-conductivity-type emitter layer.

14. A device according to claim 13, wherein a surface where said emitter electrode and first-conductivity-type emitter layer are in contact with each other is tapered with respect to said trench, thereby making an area of the contact surface larger than that when the contact surface is formed parallel to said trench.

15. A device according to claim 11, wherein in each region surrounded by said trenches,

a contact trench is formed in a region where said second-conductivity-type base layer and first-conductivity-type emitter layer are formed, and said emitter electrode is buried in said contact trench in contact with side surfaces of said second-conductivity-type base layer and side surfaces of said first-conductivity-type emitter layer on inner walls of said contact trench, and

said second-conductivity-type semiconductor layer is formed along the side walls of said trench and in contact with said emitter electrode on the inner walls of said trench, near the surface of said first-conductivity-type emitter layer.

16. A device according to claim 15, wherein said trenches are staggered into a shape of a lattice.

17. A semiconductor device comprising:

a first-conductivity-type base layer;

a second-conductivity-type emitter layer formed on a first main surface of said first-conductivity-type base layer;

a collector electrode formed in contact with a surface of said second-conductivity-type emitter layer;

a second-conductivity-type base layer formed on a second main surface of said first-conductivity-type base layer;

a plurality of trenches which extend through said second-conductivity-type base layer to reach a predetermined depth of said first-conductivity-type base layer;

a gate electrode formed in said trench via a gate insulating film;

a first-conductivity-type emitter layer selectively formed in contact with side walls of said trench, in a surface portion of said second-conductivity-type base layer;

an emitter electrode formed in contact with a surface of said second-conductivity-type base layer and a surface of said first-conductivity-type emitter layer; and

a second-conductivity-type semiconductor layer selectively formed in a region along a longitudinal direction of said trench, near the surface of said first-conductivity-type emitter layer,

wherein said plurality of trenches are formed into an annular shape, and said gate electrode is buried in said trench via said gate insulating film, and

in each region surrounded by said annular trenches,

said first-conductivity-type emitter layer is selectively formed along the side walls of said trench, in the surface portion of said second-conductivity-type base layer,

said emitter electrode is formed in contact with the surface of said second-conductivity-type base layer and the surface of said first-conductivity-type emitter layer, and

said second-conductivity-type semiconductor layer is selectively formed along the side walls of said trench, near the surface of said first-conductivity-type emitter layer.