Active load with adjustable common-mode level
First Claim
1. A differential amplifier, comprising:
- a first stage configured to receive a differential input signal; and
a second stage, coupled to an output of the first stage, including;
an active load having a transistor pair that provides a differential output signal at respective output terminals of the active load; and
a bias circuit that provides bias voltages to the transistor pair in the active load, and configured to provide an adjustable common-mode voltage at respective output terminals of the active load.
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Accused Products
Abstract
A differential preamplifier includes an active load with adjustable common-mode output level. The active load includes a transistor pair, a resistor pair, and a current source. The transistor load is employed to provide high gain, low offset, and a large bandwidth for the differential preamplifier. The resistor pair and current source are used to increase the common-mode output level of the differential preamplifier and to bias the transistor load. The current source can be varied to provide an adjustable common-mode output level suitable for driving next stage devices. The active load design allows the differential preamplifier to operate using only low power voltage supplies and with small-sized transistors.
14 Citations
30 Claims
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1. A differential amplifier, comprising:
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a first stage configured to receive a differential input signal; and
a second stage, coupled to an output of the first stage, including;
an active load having a transistor pair that provides a differential output signal at respective output terminals of the active load; and
a bias circuit that provides bias voltages to the transistor pair in the active load, and configured to provide an adjustable common-mode voltage at respective output terminals of the active load. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A differential amplifier, comprising:
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a first transistor pair configured to receive a differential input signal; and
an active load, coupled to the first transistor pair, including;
a second transistor pair that provides a differential output signal at respective output terminals of the active load; and
a bias circuit that provides bias voltages to the second transistor pair, and configured to provide an adjustable common-mode voltage at respective output terminals of the active load. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. In a differential amplifier having an active load, the active load including a first resistor coupled between a common node and a first output terminal of the active load and a second resistor coupled between the common node and a second output terminal of the active load, a method of providing an adjustable common-mode voltage at the respective output terminals of the active load, the method comprising the steps of:
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(a) biasing the active load using a current source coupled to the active load at the common node; and
(b) adjusting the current source to provide desired voltage drops across the first and second resistors, wherein respective voltage drops across the first and second resistors provide a desired common-mode voltage at the output terminals of the active load. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A two stage differential amplifier having active loads with adjustable common-mode output voltages, comprising:
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a differential amplifier input and a differential amplifier output;
a first differential amplifier stage including a first transistor pair, respective sources of the first transistor pair connected to a first current supply, respective gates of the first transistor pair connected to the differential amplifier input, respective drains of the first transistor pair connected to a first active load;
a second differential amplifier stage including a second transistor pair, respective sources of the second transistor pair connected to a second current supply, respective gates of the second transistor pair connected to the respective drains of the first transistor pair and forming a first differential amplifier stage output, respective drains of the second transistor pair connected to a second active load; and
a feedback resistor pair connecting the respective gates of the second transistor pair to the respective drains of the second transistor pair;
wherein;
the first active load includes a third transistor pair and a first active load resistor pair, respective sources of the third transistor pair connected to a first supply voltage, respective drains of the third transistor pair connected to the respective drains of the first transistor pair, respective gates of the third transistor pair connected to a third current source, the first active load resistor pair connecting the respective gates of the third transistor pair to the respective drains of the third transistor pair;
the second active load includes a fourth transistor pair and a second active load resistor pair, respective sources of the fourth transistor pair connected to a second supply voltage, respective drains of the fourth transistor pair connected to the respective drains of the second transistor pair, respective gates of the fourth transistor pair connected to a fourth current source, the second active load resistor pair connecting the respective gates of the fourth transistor pair to the respective drains of the fourth transistor pair; and
the differential amplifier output is taken from the drains of the fourth transistor pair. - View Dependent Claims (25, 26, 27, 28, 29)
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30. A differential amplifier having an active load with adjustable common-mode output voltage, comprising:
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a differential amplifier input and a differential amplifier output; and
a first transistor pair, respective sources of the first transistor pair connected to a first current supply, respective gates of the first transistor pair connected to the differential amplifier input, respective drains of the first transistor pair connected to an active load;
wherein;
the active load includes a second transistor pair and an active load resistor pair, respective sources of the second transistor pair connected to a first supply voltage, respective drains of the second transistor pair connected to the respective drains of the first transistor pair, respective gates of the second transistor pair connected to a second current source, the active load resistor pair connecting the respective gates of the second transistor pair to the respective drains of the second transistor pair; and
the differential amplifier output is taken from the drains of the second transistor pair.
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Specification