Virtual extended display information data (EDID) in a flat panel controller

• US 20060082587A1
• Filed: 02/18/2005
• Published: 04/20/2006
• Est. Priority Date: 10/18/2004
• Status: Active Grant

• Current Assignee: Genesis Microchip Inc. (STMicroelectronics NV)
• Original Assignee: Genesis Microchip Inc. (STMicroelectronics NV)
• Inventors: Noorbakhsh, Ali, Lattanzi, John, Keene, David, Chilukuri, Ram
• Granted Patent: US 7,911,475 B2
• Time in Patent Office: Days
• US Class Current: 345/544
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2370/047 using display data channel standard [DDC] communication
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.

Claims

1. A method of partitioning memory space of a single memory device in a display controller having a number of data ports each capable of being connected to an appropriate type video source and a processor arranged to process executable instructions and associated data, comprising:

allocating a first portion of the memory space for storing the executable instructions and associated data; and

allocating a second portion of the memory space for storing extended display information data, wherein the first and the second portions are always available for access by the data ports and/or the processor regardless of a power state of the display controller.

2. A method as recited in claim 1, wherein the allocating the second portion of the memory space comprises:

allocating a third portion of the second portion of the memory space for storing analog extended display information data; and

allocating a fourth portion of the second portion of the memory space for storing digital extended display information data.

3. A method as recited in claim 2, wherein some of the data ports are analog data ports and some of the data ports are digital data ports.

4. A method as recited in claim 3, wherein the analog data ports selectively retrieve the analog extended display information data.

5. A method as recited in claim 3, wherein the digital data ports selectively retrieve the digital extended display information data.

6. A method as recited in claim 1, further comprising:

providing power to the memory device by the host device by way of selected ones of the data ports in a power_off mode; and

providing power to the memory device by on-board power supply only in a power_on mode.

7. A method as recited in claim 1, wherein the data ports are each connected to the memory device by way of I2C compliant data busses.

8. A method as recited in claim 7, further comprising:

arbitrating retrieving appropriate EDID from the memory device by the requesting port and processor memory access requests so as to maintain I2C compliance.

9. A method as recited in claim 8, wherein the digital port is a DVI port and wherein the analog port is a VGA port.

10. A method as recited in claim 9, further comprising:

determining if the display is a digital display or an analog display;

activating the appropriate port based upon if the display is analog or digital, and

accessing the appropriate portion of the single memory device based upon if the display is analog or digital.

11. A display controller coupled to a display device by way of a display interface and to a host device by way of a number of data ports, comprising:

a processor arranged to process executable instructions and associated data; and

a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device that is always available for access by the data ports and/or the processor regardless of a power state of the display controller.

12. A display controller as recited in claim 11, further comprising:

a bridge portion coupling the data ports and the single memory device, wherein the bridge portion and the single memory device are both powered by the host device such that the host device can access and retrieve the appropriate EDID from the single memory device as needed in a power_down mode.

13. A controller as recited in claim 11, wherein the single memory device is a non-volatile random access memory device.

14. A controller as recited in claim 11, wherein the display controller is a dual port controller suitably arranged to control an analog type display and/or a digital type display.

15. A controller as recited in claim 11, wherein the portion of the single memory device allocated for storage of the EDID is further partitioned into an analog EDID portion and a digital EDID portion.

16. A controller as recited in claim 15, further comprising:

a display type determinator arranged to determine if the display is an analog or digital display; and

a port activator coupled to the display type determinator arranged to activate an appropriate one of the ports based on the results of the determination of the display type.

17. Computer program product for acquiring EDID from a single memory device used to concurrently store the EDID and executable instructions and associated data in an EDID compliant display controller by a host device coupled thereto by way of a requesting port, comprising:

computer code for supplying power to the memory device from the host device by way of the requesting port during boot up when the display controller is powered down;

computer code for retrieving the EDID stored in the single memory device;

computer code for passing the retrieved EDID to the requesting port;

computer code for acquiring the EDID by the host device from the requesting port; and

computer readable medium for storing the computer code.

18. Computer program product as recited in claim 17, wherein the controller is coupled to a processor arranged to process executable instructions and associated data as required.

20. Computer program product as recited in claim 18, further comprising:

computer code for partitioning the memory device into a first partition and a second partition wherein the first partition is allocated for storage of the executable instructions and associated data and wherein the second portion is allocated for storage of the EDID.

21. Computer program product as recited in claim 20, wherein the controller is a dual port controller having a first type port and a second type port wherein one of the ports is the requesting port.

22. Computer program product as recited in claim 20, further comprising:

computer code for further partitioning the second portion allocated for storage of the EDID to a third portion allocated for storage of a first type EDID corresponding to the first type port and a second type EDID corresponding to the second type port.

23. Computer program product as recited in claim 22, wherein the first type port is a DVI port and wherein the second type port is a VGA port.

24. Computer program product as recited in claim 23, further comprising:

computer code for determining if the display is a digital display or an analog display;

computer code for activating the appropriate port based upon if the display is analog or digital, and

computer code for accessing the appropriate portion of the memory device based upon if the display is analog or digital.