Digital PWM controller with efficiency optimization as a function of PWM duty cycle

• US 20060083037A1
• Filed: 12/01/2005
• Published: 04/20/2006
• Est. Priority Date: 07/27/2004
• Status: Abandoned Application

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Leung, Ka Y., Leung, Kafai, Fosler, Ross M., Wei, Chia Ling
• Application Number:
  US11/291,648
• Publication Number:
  US 20060083037A1
• Time in Patent Office: Days
• US Class Current: 363/98
• CPC Class Codes: H02M 3/33576 having at least one active switching element at the secondary side of an isolation transformer

Abstract

A method for optimizing the efficiency of a digital power supply having at least one switch for connecting an input voltage to an input node for driving an inductive storage element connected to an out put node tp provide a regulated output voltage, and a second switch for shunting the intermediate node to ground in a complementary operation. Complementary switch control signals are generated for controlling the operation of the first and second switches, wherein the ratio of the on and off time of the first switch determines the ratio of the output voltage to the input voltage. The duty cycle is then controlled to provide a regulated voltage on the output node. A delay circuit provides a delay between the time the first switch is turned off and the second switch is turned on. For a given load, the delay is varied and then a minima for the delay is determined to provide the minimum duty cycle for the given load.

Claims

1. A method for optimizing the efficiency of a switching power supply having at least one switch for connecting an input voltage to an input node for driving an inductive storage element connected to an out put node to provide a regulated output voltage, and a second switch for shunting the intermediate node to a reference voltage in a complementary mode of operation, comprising the steps of:

generating complementary switch control signals for controlling the operation of the first and second switches, wherein the ratio of the on time of the first switch to the period of a switching cycle determines the ratio of the output voltage to the input voltage;

controlling the duty cycle to provide a regulated voltage on the output node; and

providing a delay between the time one of the first and second switches is transitioned and the other of the first and second switches is transitioned;

for a given operating condition;

varying the delay, and

determining the delay that provides the minimum duty cycle for the given operating condition.

2. A method for optimizing the efficiency of a switched power supply having a plurality of switches responsive to generated pulse control signals, one switch of which is turned on and off to drive an inductive element in the power supply from an input voltage, the duty cycle of the one switch defining the ratio of the output voltage to an input voltage, comprising the steps of:

varying the initiation of conduction in at least another of the switches relative to the conduction in the one of the switches by controlling when an edge in an associated one of the pulse control signals is generated;

determining a minima in the duty cycle for a given operating condition of the power supply over the step of varying; and

after the step of determining, freezing the configuration of the respective pulse control signals at the minima.

3. The method of claim 2, wherein the one of the switches and the another of the switches constitute a complementary pair of switches in operation, such that, operationally, the one of the switches in the complementary pair is changed from a conducting state to a non conducting state in response to a first pulse edge associated with one of the pulse control signals and the other of the switches therein changes from a non conducting state to a conducting state in response to a second pulse edge associated with one of the pulse control signals and the step of varying is operable vary the relative time between generation of the first and second pulse edges.

4. The method of claim 3, wherein the step of varying is operable to cause the second step to occur prior to the occurrence of the first edge at one extreme ad to occur after the first pulse edge at another extreme.

5. The method of claim 3, wherein each of the first and second pulse edges are generated independent of the other.

6. The method of claim 5, wherein an edge configuration register is provided for containing programming information for determining the position of the associated edge within a switching cycle of the power supply, such that the step of varying is operable to alter the contents of the configuration register for at least one of the pair of switches and the step of freezing comprises latching the contents of the configuration register for the at least one of the pair of switches after the step of determining.

7. The method of claim 2, wherein the digital power supply includes a digital controller for generating the pulse control signals and wherein the steps of varying, determining and freezing occurs in response to a power up signal that initiates operation of the digital controller.

8. A method for optimizing the operation of a pulse width modulated power supply having a plurality of switches, of which at least two are complementary switches, one switch of which is turned on and off to drive an inductive element in the power supply from an input voltage, the duty cycle of the one switch defining the ratio of the output voltage to an input voltage, comprising the steps of:

generating a plurality of pulse control signals, each operable to turn on and off respective ones of the switches;

controlling the pulse width of each of the pulse control signals with a controller to define the duty cycle thereof to define the ratio between the output and input voltages;

parameterizing the operation of the controller with a processor for applying predetermined parameters to the controller to define the operation thereof;

operating the processor in an optimization mode by;

determining the optimum dead time between the time that one of the two complementary switches changes to a non conductive state prior to the other of the complementary switches changing to the conductive state in order to minimize the duty cycle for a given operating condition; and

utilizing the determined optimized dead time as a parameter for normal operation of the processor.

9. The method of claim 8, wherein the step of determining comprises the steps of:

varying the dead time;

determining a minima in the duty cycle over the step of varying; and

after the step of determining, freezing the configuration of the respective pulse control signals at the minima as a parameter for use by the processor.

10. The method of claim 8, wherein each of the pulse control signals in the step of generating is generated separately and each of the edges in the associated pulse control signals is individually controlled by the processor.

11. The method of claim 10, wherein the step of controlling the pulse width with respect to the pulse control signals associated with the two complementary switches comprises controlling the time that the leading edge of the other of the complementary switches occurs relative to the occurrence of the one of the complementary switches, the difference therebetween comprising the dead time.

12. The method of claim 11, wherein the step of determining includes controlling the edge of the other of the complementary switches to vary the dead time from one extreme to decrease the dead time from a nominal starting value to the opposite extreme to increase the dead time.

13. The method of claim 12, wherein the one extreme is negative, such that the leading edge of the other of the complementary switches occurs prior to the trailing edge of the one of the complementary switches.

14. A pulse width modulated power supply having a plurality of switches, of which at least two are complementary switches that require a dead time between the conduction of one to the conduction of the other, one switch of which is turned on and off to drive an inductive element in the power supply from an input voltage, the duty cycle of the one switch defining the ratio of the output voltage to an input voltage, comprising:

a pulse width modulator (PWM) for generating a plurality of pulse control signals, each operable to turn on and off the one of the switches at the duty cycle;

a controller for controlling said PWM to define the pulse width of each of the pulse control signals and the duty cycle;

a processor for parameterizing the operation of the controller for applying predetermined parameters to the controller to define the operation thereof;

an optimizer for operating the processor in a dead time optimization mode by determining the optimum dead time between the time that one of the two complementary switches changes to a non conductive state prior to the other of the complementary switches changing to the conductive state in order to minimize the duty cycle for a given operating condition on the power supply; and

said processor utilizing the determined optimized dead time as a parameter for normal operation of the controller.

15. The power supply of claim 14, wherein said optimizer comprises:

said processor varying the dead time;

said processor determining a minima in the duty cycle over the range that the dead time is varied; and

said processor freezing the configuration of the respective pulse control signals at the minima as a parameter for use by said processor.

16. The power supply of claim 14, wherein each of the pulse control signals in said PWM is generated separately and each of the edges in the associated pulse control signals is individually controlled by said processor.

17. The power supply of claim 16, wherein said processor controls the pulse width with respect to the pulse control signals associated with the two complementary switches by controlling the time that the leading edge of the other of the complementary switches occurs relative o the occurrence of the one of the complementary switches.

18. The power supply of claim 17, wherein said processor controls the edge of the other of the complementary switches to vary the dead time from one extreme to decrease the dead time from a nominal starting value to the opposite extreme to increase the dead time.

19. The power supply of claim 18, wherein the one extreme is negative, such that the leading edge of the other of the complementary switches occurs prior to the trailing edge of the one of the complementary switches.

20. The power Supply of claim 14, and further comprising circuitry for initiating the operation of said optimizer.