Spintronic devices with integrated transistors

• US 20060083088A1
• Filed: 06/06/2005
• Published: 04/20/2006
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Katti, Romney R., Zhu, Theodore
• Granted Patent: US 7,339,818 B2
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell

Abstract

The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Claims

1. A memory device comprising:

a semiconductor substrate having a first surface;

at least one integrated latch memory component formed on the first surface of the semiconductor substrate, wherein the at least one integrated latch memory component stores a selective logic state having a volatile memory status; and

at least one spin dependent logic device formed on the semiconductor substrate, wherein the at least one spin dependent logic device is interconnected to the at least one integrated latch memory component so as to permit a non-volatile application to the selective logic state having a volatile memory status.

2. The device of claim 1, wherein the memory device is a static random access memory (SRAM) device.

3. The device of claim 1, wherein the semiconductor substrate comprises silicon.

4. The device of claim 1, wherein the integrated latch memory component comprises at least one inverter circuit.

5. The device of claim 4, wherein the at least one inverter circuit utilizes complementary metal-oxide semiconductor (CMOS) technology.

6. The device of claim 1, wherein the selective logic state is a binary logic state.

7. The device of claim 1, wherein the volatile memory status is defined as an unstable data retention status that is power dependent.

8. The device of claim 1, wherein the non-volatile memory status is defined as a stable data retention status that is power independent.

9. The device of claim 1, wherein the at least one spin dependent logic device utilizes a selectable resistance differential to store the selective logic state.

10. The device of claim 1, wherein the at least one spin dependent logic device is a giant magneto-resistance (GMR) device.

11. The device of claim 10, wherein the GMR device comprises a device having a first pinned layer of a magnetic material that is magnetized in a first fixed direction and a second layer of magnetic material that may be magnetized in either the first fixed direction or a second direction.

12. The device of claim 11, wherein the first pinned layer is a magnetic material selected from the group consisting of NiFeCo, NiFe, CoFe, Cu, Co, Ni, Fe, and Ta.

13. The device of claim 11, wherein the second layer is a magnetic material selected from the group consisting of NiFeCo, NiFe, CoFe, Cu, Co, Ni, Fe, and Ta.

14. An SRAM device formed on a semiconductor substrate, the SRAM device comprising:

a plurality of MOSFET devices formed on a first surface of the semiconductor substrate, wherein the plurality of MOSFET devices are logically interconnected so as to store a logic state with a volatile status; and

at least one spin dependent logic device formed on the first surface of the semiconductor substrate, wherein the at least one spin dependent logic device is electrically interconnected to the plurality of MOSFET devices so as to provide a non-volatile operation of the SRAM device, wherein the logic state is stored with a non-volatile logic status.

15. A static memory device formed on a semiconductor substrate, the static memory device comprising:

a plurality of solid state components formed on the semiconductor substrate and logically interconnected to temporarily store a logic state having a power dependent storage status; and

at least one integrated magneto-resistive component formed on the first surface of the semiconductor substrate and electrically interconnected to the plurality of solid state components, wherein the at least one integrated magnetic component provides a non-volatile storage status to the logic state.

16. An integrated memory device comprising:

a volatile memory component logically configured to temporarily store a selective logic state; and

a non-volatile memory component integrated with the volatile memory component to independently store the selective logic state as a measured resistance differential across the non-volatile memory component in a manner so as to prevent the loss of the selective logic state during a power interrupt.

17. A method for preserving a selective logic state with a power dependent status, the method comprising:

logically interconnecting a plurality of MOSFET devices on a first surface of a semiconductor substrate to temporarily store a selective logic state with a power dependent status; and

integrating at least one magneto-resistive device with the plurality of MOSFET devices to independently store the selective logic state in a manner so as to prevent the loss of the selective logic state during a power interruption.