Initial synchronization acquiring device and method for parallel processed DS-CDMA UWB system and DS-CDMA system's receiver using the same

• US 20060083269A1
• Filed: 02/25/2005
• Published: 04/20/2006
• Est. Priority Date: 10/19/2004
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kim, Chae Kyu, Park, Kwang Roh, Choi, Sangsung, Lee, Jeong Goo, Kang, Kyu Min, Kang, Bub Joo
• Granted Patent: US 7,623,562 B2
• Time in Patent Office: Days
• US Class Current: 370/509
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence
• CPC Class Codes: H04B 1/7183 Synchronisation

Abstract

Provided are an initial synchronization acquiring device and method in a parallel processed DS-CDMA UWB system and a DS-CDMA UWB system'"'"'s receiver using the same. The initial synchronization acquiring device is constructed to include a correlator for correlating input signals and outputting correlation result values and an initial synchronizer for tuning initial symbol synchronization and frame synchronization by using the correlation result values received from the correlator and then storing combining mark values and a synchronization position value in a register, thereby making it possible to greatly decrease a system'"'"'s complexity, compared to the existing method of separately designing respective modules for acquiring packet synchronization and symbol synchronization in the existing CDMA system. Also, the initial synchronization acquiring device and method additionally compensates a synchronization error caused by a frequency offset generated between clocks used by a transmitter and a receiver and thereby can be efficiently used in the high-speed and parallel-processed DS-CDMA UWB system.

Claims

1. An initial synchronization acquiring device in a parallel processed DS-CDMA UWB system, the device comprising:

a correlator for correlating input signals and outputting correlation result values; and

an initial synchronizer for tuning initial symbol synchronization and frame synchronization by using the correlation result values received from the correlator and then storing combining mark values and a synchronization position value in a register.

2. The device of claim 1, wherein the correlator comprises:

a buffer for storing an inputted complex value; and

a correlation operator for correlating distribution values of the complex value from the buffer with a ternary code and thereby outputting a correlation result value.

3. The device of claim 2, wherein the correlation operator comprises:

a real part correlation operator for receiving a real part input value from the distribution values of the complex value; and

an imaginary part correlation operator for receiving an imaginary part input value from the distribution values of the complex value.

4. The device of claim 3, wherein the real part correlation operator comprises:

a multiplier for multiplying the real part input value by the ternary code; and

an adder for adding values outputted from the multiplier and thereby outputting a real part correlation result value.

5. The device of claim 3, wherein the imaginary part correlation operator comprises:

a multiplier for multiplying the imaginary part input value by the ternary code; and

an adder for adding values outputted from the multiplier and thereby outputting an imaginary part correlation result value.

6. The device of claim 1, wherein the initial synchronizer comprises:

a synchronization discriminator for determining whether signals received from the correlator are synchronized and then outputting result values; and

a combining mark/synchronization position detector for storing the result values received from the synchronization discriminator in a buffer and then, if combining mark values within the buffer are changed, obtaining a synchronization position value and storing the obtained synchronization position value and combining mark values in a register.

7. The device of claim 6, wherein the synchronization discriminator comprises:

a multiplier for receiving a plurality of input signals upon reception of despread complex values from the correlator and then respectively multiplying the input signals by preamble patterns received from a symbol matched filter;

a coherent combining adder for coherently combining multiplication values received from the multiplier and thereby outputting M pairs of coherent combining result values;

an energy calculator for calculating M energy values by using the coherent combining result values received from the coherent combining adder;

a noncoherent combining adder for noncoherently combining the M energy values received from the energy calculator and thereby outputting a noncoherent combining result value;

a comparator for comparing the noncoherent combining result value received from the noncoherent combining adder with a threshold value, and then, if the noncoherent combining result value is identical to or below the threshold value, continuously performing a filtering function with a predetermined preamble pattern, and, if the noncoherent combining result value is above the threshold value, resetting a N×

M symbol out of a N×

M+A symbol period as a preamble pattern and performing a filtering function with the reset preamble pattern, the ‘

A’

being a positive integer;

a max finder for measuring the energy values received through the noncoherent combining adder and then storing up to P (P≧

1) grade discrimination result values and thereby determining whether synchronization is performed; and

a max storage for storing the up to P-grade discrimination result values received from the max finder.

8. An initial synchronization acquiring method in a parallel processed DS-CDMA UWB system, the method comprising the steps of:

(a) correlating input signals and outputting correlation result values;

(b) performing a symbol synchronization combining with respect to a reception signal of the correlation result values and then outputting a combining result value;

(c) calculating an energy value by using the combining result value and performing a noncoherent combining with respective to the calculated energy value and thereby outputting a discrimination result value; and

(d) storing the discrimination result value in a buffer and then, if combining mark values within the buffer are changed, obtaining a synchronization position value and storing the obtained synchronization position value and combining mark values in a register.

9. The method of claim 8, wherein the step (b) respectively multiplies successive symbol input signals by preamble patterns received from a matched filter and coherently combines the multiplication result values.

10. A receiver using an initial synchronization acquiring device in a parallel processed DS-CDMA UWB system, the receiver comprising:

an ADC (analog-to-digital converter) for receiving an analog signal into which a signal received from a transmitter is baseband-converted by an RF (Radio Frequency) processing block of a receiver, and then converting the analog signal into a digital signal;

a correlator for correlating the digital signals received from the ADC and outputting correlation result values; and

an initial synchronizer for tuning initial symbol synchronization and frame synchronization by using the correlation result values received from the correlator and then storing combining mark values and a synchronization position value in a register.

11. The receiver of claim 10, wherein the correlator comprises:

a buffer for storing an inputted complex value; and

a correlation operator for correlating distribution values of the complex value from the buffer with a ternary code and thereby outputting a correlation result value.

12. The receiver of claim 11, wherein the correlation operator comprises:

a real part correlation operator for receiving a real part input value from the distribution values of the complex value; and

an imaginary part correlation operator for receiving an imaginary part input value from the distribution values of the complex value.

13. The receiver of claim 12, wherein the real part correlation operator comprises:

a multiplier for multiplying the real part input value by the ternary code; and

an adder for adding values outputted from the multiplier and thereby outputting a real part correlation result value.

14. The receiver of claim 12, wherein the imaginary part correlation operator comprises:

a multiplier for multiplying the imaginary part input value by the ternary code; and

an adder for adding values outputted from the multiplier and thereby outputting an imaginary part correlation result value.

15. The receiver of claim 10, wherein the initial synchronizer comprises:

a synchronization discriminator for determining whether signals received from the correlator are synchronized and then outputting result values; and

a combining mark/synchronization position detector for storing the result values received from the synchronization discriminator in a buffer and then, if combining mark values within the buffer are changed, obtaining a synchronization position value and storing the obtained synchronization position value and combining mark values in a register.

16. The receiver of claim 15, wherein the synchronization discriminator comprises:

a multiplier for receiving a plurality of input signals upon reception of despread complex values from the correlator and then respectively multiplying the input signals by preamble patterns received from a symbol matched filter;

a coherent combining adder for coherently combining multiplication values received from the multiplier and thereby outputting M pairs of coherent combining result values;

an energy calculator for calculating M energy values by using the coherent combining result values received from the coherent combining adder;

a noncoherent combining adder for noncoherently combining the M energy values received from the energy calculator and thereby outputting a noncoherent combining result value;

a comparator for comparing the noncoherent combining result value received from the noncoherent combining adder with a threshold value, and then, if the noncoherent combining result value is identical to or below the threshold value, continuously performing a filtering function with a predetermined preamble pattern, and, if the noncoherent combining result value is above the threshold value, resetting a N×

M symbol out of a N×

M+A symbol period as a preamble pattern and performing a filtering function with the reset preamble pattern, the ‘

A’

being a positive integer;

a max finder for measuring the energy values received through the noncoherent combining adder and then storing up to P (P≧

1) grade discrimination result values and thereby determining whether synchronization is performed; and

a max storage for storing the up to P-grade discrimination result values received from the max finder.