Circuitry for a receiving system with improved directivity and signal to noise ratio

• US 20060084405A1
• Filed: 06/06/2005
• Published: 04/20/2006
• Est. Priority Date: 12/03/1998
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Chi Development Mgmt Ltd XIX LLC (Intellectual Ventures LLC)
• Inventors: Smith, Harry B.
• Granted Patent: US 7,389,092 B2
• Time in Patent Office: Days
• US Class Current: 455/296
• CPC Class Codes: H01Q 3/26 varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture H01Q3/12, H01Q3/22, H01Q3/24 take precedence
• CPC Class Codes: H04B 7/0857 using maximum ratio combining techniques, e.g. signal-to- interference ratio [SIR], received signal strenght indication [RSS]

Abstract

A receive system, including special integrated circuits, for providing enhanced directivity in the form of a narrowed receive beam and a relatively small antenna with performance comparable to a much larger antenna at similar frequencies. Received signals are converted to digital values and stored in a manner which enables subsequent processing directed to improving the resolution of the received signals and to reduce the associated noise corresponding to the received data samples. The Signal-to-Noise ratio of the received data signals is improved as a result of processing techniques made possible by the configuration of the antenna and the digitally stored nature of the received data.

Claims

1. An integrated circuit device operable to perform an iterative processing method, said device comprising:

means for injecting a series of predetermined digital values;

means for storing new digital values resulting from said injection of digital values, said stored new digital values constituting a stored topographical number matrix in which two, or more, rows accommodate each of a plurality of trials of each of a plurality of iterative steps and wherein each iterative step introduces a number probe which causes a relative displacement between two rows, each of which contains column information, to afford an opportunity to match the stored entry values in two appropriate columns by a digital number comparator.

2. A device according to claim 1 wherein the polarity and magnitude of a next iterative probe are determined to control a next iterative result and the algebraic sum of said probes values provides an accurate estimate of the polarity and magnitude of the noise portion of each separate iterative signal-to-noise sample thereby allowing the noise to be subtracted from the delayed signal-plus-noise input to yield an enhanced signal with reduced noise.

3. A device according to claim 2 wherein each frame of signal information is enhanced by several iterative steps that reduce the noise by providing the device with the information such that each iteration results in a noise value that is either closer to, or further from, a topocentric or zero reference of an array consisting of two, or more, rows, wherein one of the rows is displaced, or shifted, in column location by an amount corresponding to a dispersion amount (difference) between a noise average of a sextet or octet that provides the information from an antenna and the average of a similar entry that is closest to the noise average by comparing values in appropriate columns so that information regarding polarity and magnitude is derived with respect to each of a succession of iterative probes.

4. A device in accordance with claim 3 further comprising:

means for preserving and executing the number injections, sensing of the results in each of the two (or more) rows of the topographical number array to provide the results of selecting appropriate columns by matching nearly equal numerical column value entries from the two rows and repeating the above process for each iteration, starting each iteration with conditions resulting from the previous iteration.

5. An integrated circuit device operable to perform a method of improving an angular resolution in a receive system, said method comprising:

aggregating signal-plus-noise data output from an antenna into a plurality of groups, each group containing data having a similar phase, wherein the phase corresponding to each group is a multiple of the phase corresponding to the other groups, said multiple being determined by a spacing between right and left elements of each group from the center of the antenna array and wherein further, said groups are formed by combining data from respective right and left antenna elements and said right and left antenna elements are equidistant from a central common reference located at a center of the array of elements and corresponding to a phase angle, phi, of zero phase; and

iteratively processing the data in said group to reduce a noise portion of a signal plus noise average to determine a relatively noise-free representation of the angle, phi, associated with an arrival direction of the signal from said group by aggregating the modified Q'"'"'s and aggregating the I'"'"'s so as to be able to divide the overall digital net values of the plus and minus Q'"'"'s by the net in-phase values I so as to determine the angle from the arctangent of each Q/I quotient.

6. An integrated circuit device operable to perform a method of improving an angular resolution in a receive system, said method comprising:

aggregating signal-plus-noise data output from an antenna into a plurality of groups, each group containing data having a similar phase, wherein the phase corresponding to each group is a multiple of the phase corresponding to the other groups, said multiple being determined by a spacing between right and left elements of each group from the center of the antenna array and wherein further, said groups are formed by combining data from respective right and left antenna elements and said right and left antenna elements are equidistant from a central common reference located at a center of the array of elements and corresponding to a phase angle, phi, of zero phase;

phase multiplying said angle, phi, from each group;

with negligible phase dispersion caused by noise; and

processing the resulting vectors from the phase multiplying step from all of the groups in order to provide improved angular discrimination against signals from unwanted angle directions outside a resultant sharpened beam.

7. An integrated circuit device operable to perform a method, said method comprising:

aggregating outputs of selected right and left side elements of an antenna array to form an aggregation of signal-plus-noise voltages in digital form, said digital values being used to modify a topological number array (TNA) in several steps to form a near real time estimate of the noise for each of one or more trials; and

determining a particular entry of a subset of said aggregation that has the least absolute deviation from an average of the subset,

wherein said identified entry represents an entry whose noise is closest to the average noise component of the signal plus noise average of the aggregate group.

8. An integrated circuit device used for improving the signal-to-noise ratio of signals including a signal portion and a noise portion and which are received in a wireless receive system, the device comprising:

means for forming a topological number array (TNA) corresponding to one or more samples of the received signals;

means for digitally processing the TNA at the carrier or intermediate frequency corresponding to the frequency of the received signals and establishing an estimated magnitude and polarity of the noise associated with each sample of the received signals; and

means for subtracting each established noise estimate from its respective sample of the received signals, wherein the subtracted noise estimate includes an appropriate carrier frequency phasing to account for the time required for the digital processing.

9. An integrated circuit device as recited in claim 8 further comprising means for determining an optimum noise estimate for each sample of the received signals, wherein the optimum estimate occurs when an actual signal cycle of a respective received signal most closely matches a corresponding one or more reference cycle comprising surrogate sinusoidal cycles generated by iteratively incrementally adding different preassigned values to the respective received signal.

12. An integrated circuit device as recited in claim 9 wherein said means for determining operates on a plurality of the surrogate sinusoidal cycles in parallel.

10. An integrated circuit device comprising:

means for determining a match between adjacent positive and negative half-cycle amplitudes of a noise estimate of a received signal, wherein the positive and negative half-cycles are associated with a carrier signal of the received signal; and

means for identifying a zero signal condition within the received signal which corresponds to an optimum noise estimate.

11. An integrated circuit device comprising:

means for subtracting a noise estimate from each sample of one or more sampled sinusoidal signals;

means for determining when the amplitude of a positive half-cycle of one or more of the sinusoidal signals most closely matches the amplitude of a respective negative half-cycle of the one or more sinusoidal signals; and

means for identifying a particular one of the one or more sinusoidal signals that results in an optimal match of its corresponding positive and negative half-cycles.

13. An integrated circuit device for use in a receive system that receives and processes received signals, the device comprising:

means for acquiring a desired signal from the received signals;

means for locking the receive system with a system timing clock, wherein the timing clock is used to sample both in-phase and quadrature analog signals; and

means for establishing a zero-phase reference.

14. An integrated circuit device for processing received signals having a noise portion, the device comprising:

means for forming a topological number array (TNA) for at least two successive trials of the received signals, wherein the TNA contains data consisting of in-phase and quadrature versions of the received signals;

means for performing an iterative process on the data contained in the TNA to determine an estimate of the magnitude and polarity of the noise portion of the received signals for each trial, wherein the iterative process consists at least of successively adding a series of equally spaced values to the data and determining a particular value that causes the noise portion to change polarity; and

subtracting each estimated noise value from the received signals to obtain a noise-reduced signal.

15. An integrated circuit device as recited in claim 14, further comprising:

means for integrating a number of noise-reduced signals, wherein the integrating comprises summing the noise-reduced signals and dividing the result of the summation by the number of noise-reduced signals summed, thereby increasing, on a power basis, a signal-to-noise ratio associated with the received signals.

16. An integrated circuit device as recited in claim 15, wherein small remaining amounts of residual noise in the received signals, that are equivalent mathematically to plus and minus constants of integration, are averaged to provide a reduced amount of residual noise to further improve the signal-to-noise ratio on a power basis.

17. An integrated circuit device as recited in claim 14, wherein the amount of noise present in the noise-reduced signals is further reduced by increasing the speed at which the received signals are processed by the integrated circuit device.

18. An integrated circuit device for processing received signals in a receive system, the device comprising:

means for aggregating a plurality of digital values in digital form, the digital values being used to modify an array comprising digital representations of the received signals, the aggregation being performed in several steps to form a near real time estimate of the noise associated with the received signals; and

means for identifying a particular entry of a subset of the aggregation that has the least absolute deviation from an average of the subset,

wherein the identified entry is an entry whose noise is closest to the average noise component of a signal plus noise average of the aggregate group.

19. An integrated circuit device for processing received signals in a receive system, the device comprising:

means for configuring a numerical array of modified signal-plus-noise values representative of the received signals such that each noise portion of the signal-plus-noise values transitions through zero at a location in the array, the location being determined by the polarity and magnitude of the noise; and

means for sensing how the injection of a programmed iterative value will change a relative location within the array by sensing, in progressive steps, when each injected iterative value causes a match in the numerical values of signal-plus-noise from two rows of the numerical array to be further from, or closer to, a topocentric center of left and right portions of the array.

20. An integrated circuit device for processing received signals in a receive system, the device comprising:

means for iteratively adding digital values to an array of stored digital information that represents a numerical array of signal-plus-noise digital values, wherein the array comprises initial values that are obtained from two or more trials including random noise values combined with two signal half cycle values that are essentially equal to each other during these two trials and wherein the initial values comprise two or more respective successive samples sampled with respect to the phase reference of the system;

means for assigning the values added to be signal values or noise values; and

means for extracting phase modulation data from a carrier signal, wherein the modulation is in the form of a sinusoidal pattern between two phase excursions accomplished by a pair of carrier instances that use the same phase reference for a plurality of such pairs which are used successively to reproduce the modulation from a series of frames of enhanced information.

21. An integrated circuit device for processing received signals in a receive system, the device comprising:

means for configuring a numerical array of modified signal-plus-noise values representative of the received signals such that each noise portion of the signal-plus-noise value transitions through zero at a location in the array, the location being determined by the polarity and magnitude of the noise;

means for sensing how the injection of a programmed iterative value will change a relative location within the array by sensing, in progressive steps, when each injected iterative value causes a match in the numerical values of signal-plus-noise from two rows of the numerical array to be further from, or closer to, a topocentric center of left and right portions of the array; and

means for sensing iterative changes in a symmetrical fashion in the modified signal-plus-noise values by using plus or minus deviations nearest to the average.