Error indication in a raid memory system

• US 20060085671A1
• Filed: 12/01/2005
• Published: 04/20/2006
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Nera Innovations Limited (Atlantic IP Services Limited)
• Original Assignee: Benjamin H. Clark, Bret D. Roscoe, Christian H. Post, Dan Zink, Gary J. Piccirillo, Jeffery Galloway, Jeffrey S. Autor, Jerome J. Johnson, John E. Larson, John M. Maclaren, Patrick L. Ferguson, Robert A. Lester, Siamak Tavallaei, Tim Majni
• Inventors: Tavallaei, Siamak, Autor, Jeffrey S., Ferguson, Patrick L., Galloway, Jeffery, Johnson, Jerome J., Piccirillo, Gary J., Majni, Tim, Lester, Robert A., Roscoe, Bret D., Post, Christian H., Clark, Benjamin H., MacLaren, John M., Larson, John E., Zink, Dan
• Granted Patent: US 7,320,086 B2
• Time in Patent Office: Days
• US Class Current: 714/5
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/328 Computer systems status display G06F11/327 takes precedence
• CPC Class Codes: G06F 2211/1052 RAID padding, i.e. completing a redundancy group with dummy data

Abstract

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Claims

1-2. -2. (canceled)

4-29. -29. (canceled)

30. A computer system comprising:

a host/data controller;

a plurality of memory cartridges operably coupled to the host/data controller, each of the plurality of memory cartridges comprising a memory controller;

a command bus operably coupled between the host/data controller and the plurality of memory controllers and configured to transmit commands from the host/data controller to the plurality of memory controllers; and

error detection logic located on the command bus and configured to detect errors on the command bus.

3. The computer system, as set forth in claim 30, wherein the plurality of memory cartridges comprises five memory cartridges.

31. The computer system, as set forth in claim 30, wherein the plurality of memory cartridges form a redundant memory array.

32. The computer system, as set forth in claim 30, wherein each of the plurality of memory cartridges comprises a plurality of memory modules, each of the plurality of memory modules comprising a plurality of memory devices.

33. The computer system, as set forth in claim 32, wherein each of the plurality of memory cartridges comprises a plurality of dual inline memory modules (DIMM), each of the plurality of memory modules comprising a plurality of synchronous dynamic random access memory (SDRAM) devices.

34. The computer system, as set forth in claim 30, comprising a command bus interface coupled between the plurality of memory cartridges and the error detection logic, the command bus interface configured to facilitate the exchange of data and commands between the host/data controller and the plurality of memory cartridges.

35. The computer system, as set forth in claim 34, comprising decode logic coupled between the command bus interface and the plurality of memory cartridges and configured to translate a system address into a memory address and a memory address into a system address for associated read and write commands between the host/data controller and the plurality of memory controllers.

36. The computer system, as set forth in claim 30, wherein the error detection logic comprises an ECC algorithm.

37. The computer system, as set forth in claim 30, wherein the error detection logic is configured to correct single bit errors on the command bus.

38. The computer system, as set forth in claim 30, wherein the error detection logic is configured to detect multi-bit errors on the command bus and further configured to transmit an unrecoverable command error message to the host/data controller when an unrecoverable multi-bit error is detected on the command bus.

39. A method of exchanging information in a redundant memory system, comprising the acts of:

detecting errors on a command bus, the errors comprising one of a single bit error and a multi-bit error;

correcting any single bit errors detected on the command bus; and

generating an error message if a multi-bit error is detected on the command bus.

40. The method of exchanging information, as set forth in claim 39, wherein the act of correcting comprises the act of correcting any single bit errors detected on the command bus using an ECC algorithm.

41. The method of exchanging information, as set forth in claim 39, wherein the act of detecting errors, comprises the act of detecting errors on a command bus, the command bus operably coupled between a host/data controller and a plurality of memory cartridges configured to form a redundant memory system.

42. The method of exchanging information, as set forth in claim 41, wherein the act of generating comprises the act of generating an error message from error detection logic located on the command bus to the host/data controller.

43. The method of exchanging information, as set forth in claim 42, comprising the act of powering down the memory cartridge in which the multi-bit error is detected in response to the error message generated from the error detection logic.

44. A memory cartridge comprising:

a plurality of memory modules, each of the plurality of memory modules comprising a reserved segment of non-volatile memory configured to store information unique to the corresponding memory module; and

a memory controller configured to detect errors in each of the plurality of memory modules and configured to facilitate storage of information correlative to the errors detected in the plurality of memory modules in the respective reserved segment of non-volatile memory.

45. The memory cartridge, as set forth in claim 44, wherein the plurality of memory modules comprises a plurality of dual inline memory modules (DIMMs).

46. The memory cartridge, as set forth in claim 44, wherein each of the plurality of reserved segments of non-volatile memory is configured to store identification information corresponding to the respective memory module.

47. The memory cartridge, as set forth in claim 44, wherein each of the plurality of reserved segments of non-volatile memory comprises 128 bytes of memory.

48. The memory cartridge, as set forth in claim 44, wherein the memory controller comprises ECC logic to detect errors in each of the plurality of memory modules.

49. The memory cartridge, as set forth in claim 44, wherein the memory controller is configured to receive error information from a host/data controller, the error information correlative to errors detected in the plurality of memory modules, and wherein the memory controller is further configured to facilitate storage of the error information from the host/data controller in the respective reserved segment of non-volatile memory.

50-52. -52. (canceled)

53. A method of storing error detection information on a memory module comprising the acts of:

detecting an error on the memory module; and

storing information correlative to the error in a reserved segment of the memory module, the reserved segment comprising non-volatile memory.

54. The method of storing error detection information, as set forth in claim 53, wherein the act of detecting comprises the act of detecting an error on the memory module using an ECC algorithm.

55. The method of storing error detection information, as set forth in claim 53, wherein the act of storing comprises the act of storing an error type correlative to the type of error.

56. The method of storing error detection information, as set forth in claim 53, wherein the act of storing comprises the act of storing an address correlative to the address in which the error is detected.

57-91. -91. (canceled)