RFID tags calibrating backscattering period also for non-integer divide ratios

• US 20060086810A1
• Filed: 10/24/2005
• Published: 04/27/2006
• Est. Priority Date: 10/26/2004
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Diorio, Christopher J., Humes, Todd E., Cooper, Scott Anthony
• Granted Patent: US 7,246,751 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

An RFID tag that receives a calibration instruction from a reader can determine the basic backscatter period of the symbols to be backscattered. According to some embodiments, when the instruction includes a calibration feature that is to be divided by a divide ratio, the tag measures the duration of the feature in terms of numbers of internal pulses, resulting in a binary L-number. Then at least two versions of the L-number (PR1-number, PR2-number) are combined, so as to yield the effective result of the division alternately, even when the divide ratio is a non-integer. The backscatter period can then be determined from the BP-number and the period of the internal pulses.

Claims

1. A circuit for a radio frequency identification (RFID) tag, comprising:

a demodulator that is arranged to demodulate a waveform of a wirelessly received wave;

a processing block that includes;

a counter configured to determine an L-number from a duration of a calibration feature of the waveform, and

a combining circuit configured to combine a first nonzero version of the L-number with a second nonzero version of the L-number so as to derive a BP-number such that the derived BP-number substantially equals the L-number divided by a preset non-integer divide ratio; and

a modulator that is arranged to modulate a second wave with encoded symbols that have a periodicity determined from the BP-number.

2. The circuit of claim 1, wherein

a variable M assumes a value from a set that includes 1, 2, 4, and 8, and the symbols are encoded with the periodicity shown in FIG. 7A of this document according to the assumed value of the variable M.

3. The circuit of claim 1, wherein

the counter is arranged to:

receive a train of substantially periodic pulses; and

count features of the pulses during the calibration feature to determine the L-number.

4. The circuit of claim 1, further comprising:

a selector adapted to establish a first computation setting out of at least a first and a second available computation settings according to the divide ratio, and

wherein a first result is derived for the BP-number if the first computation setting is established, and a second result different from the first result is derived for the BP-number if the second computation setting is established.

5. The circuit of claim 4, wherein

the selector comprises at least one multiplexer.

6. The circuit of claim 4, wherein

if the second computation setting is established, the BP-number is derived by the combining.

7. The circuit of claim 6, wherein

the second result is such that the derived BP-number substantially equals the L-number divided by a preset integer divide ratio

8. The circuit of claim 4, wherein

the processing block further includes an estimator, and

if the second computation setting is established, the BP-number is derived by using the estimator without the combining.

9. The circuit of claim 1, wherein

the combining circuit comprises an adder operable to add the first version to the second version.

10. The circuit of claim 1, wherein

the combining circuit comprises a subtractor operable to subtract the second version from the first version.

11. The circuit of claim 1, wherein

combining the first version with the second version results in an intermediate number, and

the processing block further comprises a shifter operable to shift bits of the intermediate number to derive the BP-number.

12. The circuit of claim 1, wherein

the processing block further comprises an offset adder operable to add an offset to one of the first version, the second version, and the BP-number.

13. The circuit of claim 1, further comprising:

a memory operable to store at least one of the first version, the second version, and the BP-number.

14. The circuit of claim 1, wherein

one of the first version and the second version is substantially equal to the L-number.

15. The circuit of claim 1, wherein

the processing block further comprises a first generator for generating a signal that conveys the first version responsive to a signal that conveys the L-number, and

wherein the first generator is adapted to determine the first version by selecting bits of the L-number.

16. The circuit of claim 15, wherein

the processing block further comprises a second generator for generating a signal that conveys the second version responsive to a signal that conveys the L-number.

17. The circuit of claim 16, wherein

the second generator is adapted to determine the second version by selecting bits of the first version.

18. The circuit of claim 1, wherein

the first version is substantially equal to the second version.

19. The circuit of claim 1, wherein

the first version substantially equals the L-number times a first factor, and

the second version substantially equals the L-number times a second factor.

20. The circuit of claim 19, wherein

the first factor equals twice the second factor.

21. The circuit of claim 19, wherein

the first factor equals a first power of 2.

22. The circuit of claim 21, wherein

the second factor equals a second power of 2.

23. The circuit of claim 21, wherein

the processing block further comprises a shifter operable to shift bits of the L-number to derive the first version.

24. The circuit of claim 23, wherein

the shifter is operable to left-shift the bits of the L-number.

25. The circuit of claim 23, wherein

the shifter is operable to right-shift the bits of the L-number.

26. The circuit of claim 1, wherein

the processing block is further arranged to adjust the determined BP-number if an error condition is met.

27. The circuit of claim 26, wherein

the error condition is that the determined BP-number is larger than a maximum.

28. The circuit of claim 26, wherein

the error condition is that the determined BP-number is smaller than a minimum.

29. A radio frequency identification (RFID) tag, comprising:

an antenna arranged to receive a wireless wave;

a demodulator arranged to demodulate a waveform of the wirelessly received wave;

a processing block that includes;

a counter configured to determine an L-number from a duration of a calibration feature of the waveform, and

a combining circuit configured to combine a first nonzero version of the L-number with a second nonzero version of the L-number so as to derive a BP-number such that the derived BP-number substantially equals the L-number divided by a preset non-integer divide ratio; and

a modulator that is arranged to backscatter via the antenna a wave with modulation that encodes symbols that have a periodicity determined from the BP-number.

30. The tag of claim 29, wherein

the counter is arranged to:

receive a train of substantially periodic pulses; and

count features of the pulses during the calibration feature to determine the L-number.

31. The tag of claim 29, further comprising:

a selector adapted to establish a first computation setting out of at least a first and a second available computation settings according to the divide ratio, and

wherein a first result is derived for the BP-number if the first computation setting is established, and a second result different from the first result is derived for the BP-number if the second computation setting is established.

32. The tag of claim 31, wherein

if the second computation setting is established, the BP-number is derived by the combining.

33. The tag of claim 32, wherein

the second result is such that the derived BP-number substantially equals the L-number divided by a preset integer divide ratio

34. The tag of claim 31, wherein

the processing block further includes an estimator, and

if the second computation setting is established, the BP-number is derived by using the estimator without the combining.

35. The tag of claim 29, wherein

the combining circuit comprises an adder operable to add the first version to the second version.

36. The tag of claim 29, wherein

combining the first version with the second version results in an intermediate number, and

the processing block further comprises a shifter operable to shift bits of the intermediate number to derive the BP-number.

37. The tag of claim 29, wherein

the processing block further comprises an offset adder operable to add an offset to one of the first version, the second version, and the BP-number.

38. A circuit for a radio frequency identification (RFID) tag that is responsive to an RFID reader, the RFID tag comprising:

a means for demodulating a waveform from a first wireless wave received from the reader;

a means for determining an L-number from a duration of a calibration feature of the waveform;

a means for deriving a BP-number by combining a first nonzero version of the L-number with a second nonzero version of the L-number such that the derived BP-number substantially equals the L-number divided by a preset non-integer divide ratio; and

a means for modulating a second wave that is to be received by the reader by encoding symbols with a periodicity determined from the BP-number.

39. The circuit of claim 38, wherein

the deriving means comprises adding means for adding the first version with the second version.

40. The circuit of claim 38, wherein

the deriving means comprises subtracting means for subtracting the second version from the first version.

41. The circuit of claim 38, wherein

combining the first version with the second version results in an intermediate number, and

further comprising means for adjusting the intermediate number to derive the BP-number.

42. The circuit of claim 38, further comprising:

means for adding an offset to one of the first version, the second version, and the BP-number.

43. The circuit of claim 38, further comprising:

means for storing at least one of the first version, the second version, and the BP-number.

44. The circuit of claim 38, wherein

one of the first version and the second version is substantially equal to the L-number.

45. The circuit of claim 38, wherein

one of the first version and the second version is generated by selecting bits of the L-number.

46. The circuit of claim 38, wherein

the second version is generated by selecting bits of the first version.

47. The circuit of claim 38, wherein

the first version is substantially equal to the second version.

48. The circuit of claim 38, wherein

the first version substantially equals the L-number times a first factor, and

the second version substantially equals the L-number times a second factor.

49. The circuit of claim 48, wherein

the first factor equals twice the second factor.

50. The circuit of claim 48, wherein

the first factor equals a first power of 2.

51. The circuit of claim 50, wherein

the second factor equals a second power of 2.

52. The circuit of claim 50, further comprising:

means for deriving the first version by shifting bits of the L-number.

53. A method for an RFID tag, comprising:

receiving a first wireless wave having a waveform;

determining an L-number from a duration of a calibration feature of the waveform;

deriving a BP-number by combining a first nonzero version of the L-number with a second nonzero version of the L-number such that the derived BP-number substantially equals the L-number divided by a preset non-integer divide ratio; and

modulating a second wave that encodes symbols with a periodicity determined from the BP-number.

54. The method of claim 53, wherein

a variable M assumes a value from a set that includes 1, 2, 4, and 8, and

the symbols are encoded with the periodicity shown in FIG. 7A of this document according to the assumed value of the variable M.

55. The method of claim 53, further comprising:

receiving a train of substantially periodic pulses; and

counting features of the pulses during the calibration feature to determine the L-number.

56. The method of claim 53, further comprising:

establishing a first computation setting out of at least a first and a second available computation settings according to the divide ratio, and

wherein a first result is derived for the BP-number if the first computation setting is established, and a second result different from the first result is derived for the BP-number if the second computation setting is established.

57. The method of claim 56, wherein

if the second computation setting is established, the BP-number is derived by the combining.

58. The method of claim 57, wherein

the second result is such that the derived BP-number substantially equals the L-number divided by a preset integer divide ratio

59. The method of claim 56, wherein

if the second computation setting is established, the BP-number is derived without the combining.

60. The method of claim 53, wherein

combining comprises adding the first version with the second version.

61. The method of claim 53, wherein

combining comprises subtracting the second version from the first version.

62. The method of claim 53, wherein

combining the first version with the second version results in an intermediate number, and

further comprising adjusting the intermediate number to derive the BP-number.

63. The method of claim 53, further comprising:

adding an offset to one of the first version, the second version, and the BP-number.

64. The method of claim 53, further comprising:

storing at least one of the first version, the second version, and the BP-number.

65. The method of claim 53, wherein

one of the first version and the second version is substantially equal to the L-number.

66. The method of claim 53, wherein

one of the first version and the second version is generated by selecting bits of the L-number.

67. The method of claim 53, wherein

the second version is generated by selecting bits of the first version.

68. The method of claim 53, wherein

the first version is substantially equal to the second version.

69. The method of claim 53, wherein

the first version substantially equals the L-number times a first factor, and

the second version substantially equals the L-number times a second factor.

70. The method of claim 69, wherein

the first factor equals twice the second factor.

71. The method of claim 69, wherein

the first factor equals a first power of 2.

72. The method of claim 71, wherein

the second factor equals a second power of 2.

73. The method of claim 71, further comprising:

deriving the first version by shifting bits of the L-number.

74. The method of claim 73, wherein

shifting is performed by left-shifting bits of the L-number.

75. The method of claim 73, wherein

shifting is performed by right-shifting bits of the L-number.

76. The method of claim 53, further comprising:

adjusting the determined BP-number if an error condition is met.

77. The method of claim 76, wherein

the error condition is that the determined BP-number is larger than a maximum.

78. The method of claim 76, wherein

the error condition is that the determined BP-number is smaller than a minimum.