Method of forming a transistor having a dual layer dielectric

• US 20060086936A1
• Filed: 10/22/2004
• Published: 04/27/2006
• Est. Priority Date: 10/22/2004
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Hoffman, Randy, Mardilovich, Peter
• Granted Patent: US 7,265,003 B2
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Embodiments of methods, apparatuses, components, and/or systems for forming transistor having a dual layer dielectric are described.

Claims

1. A method, comprising:

forming a channel layer over at least a portion of a substrate, wherein said channel layer substantially comprises zinc indium oxide.

depositing a first material over at least a portion of a substrate by use of one or more low temperature processes to form a first portion of a dielectric layer, at least a portion of said first portion of a dielectric layer comprising inorganic dielectric material;

depositing a second material over and/or in contact with said first portion of a dielectric layer by use of one or more solution processes to form a second portion of a dielectric layer, at least a portion of said second portion of a dielectric layer comprising organic dielectric material, such as to form at least a portion of a thin film transistor (TFT).

2. The method of claim 1, wherein said first portion of a dielectric layer is formed in contact with at least a portion of said channel layer.

3. The method of claim 1, and further comprising forming a gate electrode over and/or in contact with at least a portion of said second portion of a dielectric layer.

4. The method of claim 3, and further comprising forming a source electrode and a drain electrode over at least a portion of the substrate.

5. The method of claim 4, and further comprising post-processing at least a portion of said first portion of a dielectric layer, said second portion of a dielectric layer, said channel layer, said source and drain electrodes, and/or said gate electrode.

6. The method of claim 5, wherein said post-processing comprises one or more of the following:

an annealing process and an ultraviolet (UV) curing process.

7. The method of claim 6, wherein said post-processing is performed after the deposition of a particular dielectric layer, but prior to the deposition of one or more subsequent dielectric layers.

8. The method of claim 4, and further comprising:

patterning at least a portion of said source and drain electrodes, said channel layer, said first portion of a dielectric layer, said second portion of a dielectric layer and/or said gate electrode.

9. The method of claim 4, wherein said channel layer is formed on said substrate, said source and drain electrodes are formed on at least a portion of said substrate and/or said channel layer, said first portion of a dielectric layer is formed on at least a portion of said channel layer and/or said source and drain electrodes, said second portion of a dielectric layer is formed on at least a portion of said first portion of a dielectric layer, and said gate electrode is formed on at least a portion of said second portion of a dielectric layer, such as to form at least a portion of a top gate thin film transistor.

10. The method of claim 4, wherein said gate electrode is formed on said substrate, said second portion of a dielectric layer is formed on at least a portion of said gate electrode and/or said substrate, said first portion of a dielectric layer is formed on at least a portion of said second portion of a dielectric layer, said source and drain electrodes are formed on at least a portion of said second portion of a dielectric layer, and said channel layer is formed on at least a portion of said second portion of a dielectric layer and/or said source and drain electrodes, such as to form at least a portion of a bottom gate thin film transistor.

11. The method of claim 1, wherein said solution processes comprise one or more of the following processes:

ejection, contact printing, screen printing, dip coating, and spray coating.

12. The method of claim 11, wherein said ejection process comprises a thermal inkjet process.

13. The method of claim 4, wherein said source and drain electrodes substantially comprise indium tin oxide.

14. The method of claim 3, wherein said gate electrode substantially comprises indium tin oxide.

15. The method of claim 1, wherein said channel layer substantially comprises zinc indium oxide having a Zn:

In atomic ratio approximately within the range of about 1;

1 to about 1;

8.

16. The method of claim 1, wherein said channel layer substantially comprises zinc indium oxide having a Zn:

In atomic ratio approximately within the range of about 1;

3 to about 1;

5.

17. The method of claim 1, wherein said inorganic dielectric material comprises one or more of the following:

AlO_x, SiO_x, SiN_x, SiO_xN_y, ZrO_x, TaO_x, HfO_x and combinations thereof.

18. The method of claim 1, wherein said wherein said organic dielectric material comprises one or more of the following:

UV curable monomers including UV curable acrylic monomers, acrylic polymers, thermal curable monomers, polymer solutions, melted polymer and/or oligomer solutions, poly methyl methacrylates, poly vinylphenols, benzocyclobutenes, one or more polyimides, and combinations thereof.

19. The method of claim 1, wherein said substrate comprises one or more of the following:

plastics and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polyetherimides (PEI), polycarbonates (PC), polyethylenenaphthalates (PEN), acrylics, polymethylmethacrylates (PMMA), and combinations thereof, one or more inorganic materials, including silicon, silicon dioxide, one or more types of glass, stainless steel, metal foils, including foils of aluminum and copper, and combinations thereof.

20. The method of claim 1, wherein said one or more low temperature processes are substantially performed within a range of temperature less than approximately 300 degrees Celsius.

21. The method of claim 1, wherein said one or more low temperature processes comprises one or more of the following:

vacuum deposition, including RF sputtering, DC sputtering and reactive sputtering, atomic layer deposition (ALD), and evaporation; and

one or more solution processes.

22. A method of forming a thin film transistor, comprising:

a step for forming a source and drain electrode over at least a portion of a substrate;

a step for forming a channel layer over at least a portion of the substrate, said channel layer substantially comprising zinc indium oxide.

a step for depositing a first material over at least a portion of a substrate by use of one or more steps for low temperature processing to form a first portion of a dielectric layer, at least a portion of said first material layer comprising inorganic dielectric material;

a step for depositing a second material over and/or in contact with said first portion of a dielectric layer by use of one or more steps for solution processing to form a second portion of a dielectric layer, at least a portion of said second material layer comprising organic dielectric material; and

a step for forming a gate electrode over and/or in contact with at least a portion of said second portion of a dielectric layer, such as to form at least a portion of a thin film transistor (TFT).

23. The method of claim 22, and further comprising:

a step for patterning at least a portion of said source and drain electrodes, said channel layer, said first portion of a dielectric layer, said second portion of a dielectric layer and/or said gate electrode.

24. The method of claim 22, wherein one or more steps for low temperature processing include:

vacuum deposition, including RF sputtering, DC sputtering, reactive sputtering, atomic layer deposition (ALD), and evaporation; and

one or more steps for solution processing.

25. The method of claim 24, wherein said one or more steps for solution processing comprise one or more of the following:

ejection, contact printing, screen printing, dip coating, and spray coating.

26. The method of claim 24, wherein said one or more steps for low temperature processing are substantially performed within a range of temperature less than approximately 300 degrees Celsius.

27. The method of claim 22, and further comprising post-processing at least a portion of said first portion of a dielectric layer, said second portion of a dielectric layer, said channel layer, said source and drain electrodes, and/or said gate electrode by use of at least one annealing process and/or ultraviolet (UV) curing process.

28. The method of claim 22, wherein said source and said drain electrodes at least partially comprise indium tin oxide.

29. The method of claim 22, wherein said channel layer substantially comprises zinc indium oxide having a Zn:

In atomic ratio approximately within the range of about 1;

1 to about 1;

8.

30. The method of claim 29, wherein said channel layer substantially comprises zinc indium oxide having a Zn:

In atomic ratio approximately within the range of about 1;

3 to about 1;

5.

31. The method of claim 22, wherein said inorganic dielectric material comprises one or more of the following:

AlO_x, SiO_x, SiN_x, SiO_xN_y, ZrO_x, TaO_x, HfO_x and combinations thereof.

32. The method of claim 22, wherein said wherein said organic dielectric material comprises one or more of the following:

UV curable monomers including UV curable acrylic monomers, acrylic polymers, thermal curable monomers, polymer solutions, melted polymer and/or oligomer solutions, poly methyl methacrylates, poly vinylphenols, benzocydobutenes, one or more polyimides, and combinations thereof.

33. The method of claim 22, wherein said substrate comprises one or more of the following:

plastics and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polyetherimides (PEI), polycarbonates (PC), polyethylenenaphthalates (PEN), acrylics, polymethylmethacrylates (PMMA), and combinations thereof, one or more inorganic materials, including silicon, silicon dioxide, one or more types of glass, stainless steel, metal foils, including foils of aluminum and copper, and combinations thereof.

34. An apparatus, comprising:

at least one thin film transistor (TFT) having;

a substrate;

a channel layer disposed over at least a portion of the substrate, wherein said channel layer comprises zinc indium oxide, and wherein said channel layer comprises at least a first surface and a substantially opposing second surface;

a first portion of a dielectric layer disposed adjacent to said first surface of said channel layer, wherein said first portion of a dielectric layer comprises aluminum oxide, and wherein said first portion of a dielectric layer comprises at least a first surface, disposed adjacent to said first surface of said channel layer, and a substantially opposing second surface; and

a second portion of a dielectric layer disposed adjacent to said second surface of said first portion of a dielectric layer, wherein said second portion of a dielectric layer comprises a UV curable monomer, and wherein said second portion of a dielectric layer comprises at least a first surface, disposed adjacent to said second surface of said first portion of a dielectric layer, and a substantially opposing second surface.

35. The apparatus of claim 34, and further comprising:

a source and a drain electrode disposed adjacent to and electrically coupled with said channel layer, and

a gate electrode disposed adjacent to and electrically coupled with said second surface of said second portion of a dielectric layer.

36. The apparatus of claim 35, wherein one or more of said source electrode, said drain electrode and/or said gate electrode substantially comprises indium tin oxide.

37. The apparatus of claim 34, wherein said TFT comprises a flexible TFT.

38. The apparatus of claim 34, wherein said TFT is substantially transparent.

39. The apparatus of claim 35, wherein at least a portion of said source and drain electrodes, said channel layer, said first portion of a dielectric layer, said second portion of a dielectric layer and/or said gate electrode are formed by use of one or more low temperature processes.

40. The apparatus of claim 39, wherein said one or more low temperature processes are substantially performed within a range of temperature less than approximately 300 degrees Celsius.

41. The apparatus of claim 39, wherein one or more low temperature processes include:

vacuum deposition, including RF sputtering, DC sputtering, reactive sputtering, atomic layer deposition (ALD), and evaporation; and

one or more solution processes.

42. The apparatus of claim 41, wherein said solution processes comprise one or more of the following processes:

ejection, including thermal and piezo ejection, contact printing, screen printing, dip coating, spray coating, screen printing, chemical bath deposition, and successive ionic layer absorption and reaction.

43. The apparatus of claim 34, wherein said first portion of a dielectric layer is disposed by use of one or more sputtering processes, including RF and DC sputtering.

44. The apparatus of claim 34, wherein said second portion of a dielectric layer is formed by use of one or more thermal ejection processes.

45. The apparatus of claim 34, wherein said channel layer substantially comprises zinc indium oxide having a Zn:

In atomic ratio approximately within the range of about 1;

1 to about 1;

8.

46. The apparatus of claim 34, wherein said channel layer substantially comprises zinc indium oxide having a Zn:

In atomic ratio approximately within the range of about 1;

3 to about 1;

5.

47. The apparatus of claim 34, wherein said substrate comprises one or more of:

plastics and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polyetherimides (PEI), polycarbonates (PC), polyethylenenaphthalates (PEN), acrylics including polymethylmethacrylates (PMMA), and combinations thereof, one or more inorganic materials, including silicon, silicon dioxide, one or more types of glass, stainless steel, metal foils, including foils of aluminum and copper, and combinations thereof.

48. An apparatus, comprising:

means for forming a thin film transistor (TFT) having a substrate, at least one channel layer, a plurality of electrodes, and a dielectric layer having a first portion and a second portion, wherein said channel layer substantially comprises zinc indium oxide, at least a portion of said electrodes substantially comprise indium tin oxide, said first portion of a dielectric layer substantially comprises one or more oxides, and said second portion of a dielectric layer substantially comprises one or more UV curable monomers.

49. The apparatus of claim 48, wherein said means for forming a TFT comprises a means for forming a flexible TFT.

50. The apparatus of claim 48, wherein at least a portion of said source and drain electrodes, said channel layer, said first portion of a dielectric layer, said second portion of a dielectric layer and/or said gate electrode includes means for forming at a low temperature.

51. The apparatus of claim 50, wherein said means for forming at a low temperature is substantially performed within a range of temperature less than approximately 300 degrees Celsius.

52. The apparatus of claim 51, wherein said means for forming at a low temperature include one or more of:

vacuum deposition, including RF sputtering, DC sputtering, reactive sputtering, atomic layer deposition (ALD), and evaporation; and

one or more means for solution processing.

53. The apparatus of claim 52, wherein said one or more means for solution processing comprise one or more of the following:

ejection, including thermal and piezo ejection, contact printing, screen printing, dip coating, spray coating, screen printing, chemical bath deposition, and successive ionic layer absorption and reaction.

54. The apparatus of claim 48, wherein said first portion of a dielectric layer is disposed by use of one or more sputtering processes, including RF and DC sputtering.

55. The apparatus of claim 48, wherein said second portion of a dielectric layer is formed by use of one or more thermal ejection processes.

56. The apparatus of claim 48, wherein said channel layer substantially comprises zinc indium oxide having a Zn:

In atomic ratio approximately within the range of about 1;

1 to about 1;

8.

57. The apparatus of claim 48, wherein said channel layer substantially comprises zinc indium oxide having a Zn:

In atomic ratio approximately within the range of about 1;

3 to about 1;

5.

58. The apparatus of claim 48, wherein said first portion of a dielectric layer comprises one or more of:

AlO_x, SiO_x, SiN_x, SiO_xN_y, ZrO_x, TaO_x, HfO_x and combinations thereof.

59. The apparatus of claim 48, wherein said substrate comprises one or more of the following:

plastics and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polyetherimides (PEI), polycarbonates (PC), polyethylenenaphthalates (PEN), acrylics including polymethylmethacrylates (PMMA), and combinations thereof, one or more inorganic materials, including silicon, silicon dioxide, one or more types of glass, stainless steel, metal foils, including foils of aluminum and copper, and combinations thereof.

60. The apparatus of claim 59, wherein said wherein said means for forming a TFT comprises a means for forming a substantially transparent TFT.

61. A thin film transistor (TFT), formed substantially by a process comprising:

forming a source and drain electrode over at least a portion of a substrate;

forming a channel layer over at least a portion of the substrate, said channel layer substantially comprising zinc indium oxide.

depositing a first material over at least a portion of a substrate by use of one or more low temperature processes to form a first portion of a dielectric layer, at least a portion of said first material layer comprising inorganic dielectric material;

depositing a second material over and/or in contact with said first portion of a dielectric layer by use of one or more solution processes to form a second portion of a dielectric layer, at least a portion of said second material layer comprising organic dielectric material; and

forming a gate electrode over and/or in contact with at least a portion of said second portion of a dielectric layer such that at least a portion of a thin film transistor (TFT) is formed.

62. The TFT of claim 61, wherein said source and said drain electrodes at least partially comprise indium tin oxide.

63. The TFT of claim 61, and further comprising:

patterning at least a portion of said source and drain electrodes, said channel layer, said first portion of a dielectric layer, said second portion of a dielectric layer and/or said gate electrode.

64. The TFT of claim 61, wherein at least a portion of said source and drain electrodes, said channel layer, said first and said second portions of a dielectric layer and/or said gate electrode are formed by use of one or more low temperature processes.

65. The TFT of claim 64, wherein said one or more low temperature processes are substantially performed within a range of temperature less than approximately 300 degrees Celsius.

66. The TFT of claim 64, wherein one or more low temperature processes include:

vacuum deposition, including RF sputtering, DC sputtering, reactive sputtering, atomic layer deposition (ALD), and evaporation; and

one or more solution processes.

67. The TFT of claim 64, wherein said one or more solution processes comprise one or more of the following:

ejection, contact printing, screen printing, dip coating, spray coating, screen printing, chemical bath deposition, and successive ionic layer absorption and reaction.

68. The TFT of claim 61, wherein said one or more vacuum deposition processes comprise one or more of the following:

sputtering, including RF sputtering;

atomic layer deposition (ALD); and

evaporation.

69. The TFT of claim 61, and further comprising post-processing at least a portion of said first portion of a dielectric layer, said second portion of a dielectric layer, said channel layer, said source and drain electrodes, and/or said gate electrode by use of at least one annealing process and/or ultraviolet (UV) curing process.

70. The TFT of claim 61, wherein said channel layer substantially comprises zinc indium oxide having a Zn:

In atomic ratio approximately within the range of about 1;

1 to about 1;

8.

71. The TFT of claim 70, wherein said channel layer substantially comprises zinc indium oxide having a Zn:

In atomic ratio approximately within the range of about 1;

3 to about 1;

5.

72. The TFT of claim 61, wherein said inorganic dielectric material comprises one or more of the following:

AlO_x, SiO_x, SiN_x, SiO_xN_y, ZrO_x, TaO_x, HfO_x and combinations thereof.

73. The TFT of claim 61, wherein said wherein said organic dielectric material comprises one or more of the following:

UV curable monomers including UV curable acrylic monomers, acrylic polymers, thermal curable monomers, polymer solutions, melted polymer and/or oligomer solutions, poly methyl methacrylates, poly vinylphenols, benzocyclobutenes, one or more polyimides, and combinations thereof.

74. The TFT of claim 61, wherein said substrate comprises one or more of the following:

plastics and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polyetherimides (PEI), polycarbonates (PC), polyethylenenaphthalates (PEN), acrylics including polymethylmethacrylates (PMMA), and combinations thereof, one or more inorganic materials, including silicon, silicon dioxide, one or more types of glass, stainless steel, metal foils, including foils of aluminum and copper, and combinations thereof.