Impedance adjustment circuits and methods using replicas of variable impedance circuits

• US 20060087339A1
• Filed: 10/11/2005
• Published: 04/27/2006
• Est. Priority Date: 10/11/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Hoe-ju, Lee, Jae-jun, Kim, Kyu-hyoung
• Granted Patent: US 7,295,033 B2
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching

Abstract

An impedance adjustment circuit for controlling an impedance of a variable impedance circuit includes a calibration circuit including a replica of the variable impedance circuit and configured to generate an impedance control signal for the variable impedance circuit based on a voltage generated at the replica of the variable impedance circuit in response to a reference current. The calibration circuit may be configured to generate the reference current based on a reference resistor coupled thereto. In particular, the calibration circuit may be configured to match a current in the replica of the variable impedance circuit and a current in the reference resistor to generate the voltage at the replica of the variable impedance circuit.

Claims

1. An impedance adjustment circuit for controlling an impedance of a variable impedance circuit, the comprising:

a calibration circuit including a replica of the variable impedance circuit and configured to generate an impedance control signal for the variable impedance circuit based on a voltage generated at the replica of the variable impedance circuit in response to a reference current.

2. An impedance adjustment circuit according to claim 1, wherein the calibration circuit is configured to generate the reference current based on a reference resistor coupled thereto.

3. An impedance adjustment circuit according to claim 2, wherein the calibration circuit is configured to match a current in the replica of the variable impedance circuit and a current in the reference resistor.

4. An impedance adjustment circuit according to claim 2, wherein the variable impedance circuit comprises a pull-up circuit and/or a pull-down circuit coupled to an external signal node of an integrated circuit device.

5. An impedance adjustment circuit according to claim 2:

wherein the variable impedance circuit comprises a pull-down circuit and a pull-up circuit connected to a signal node configured to be connected to an external source and/or load;

wherein the replica of the variable impedance circuit comprises a replica of the pull-down circuit and a replica of the pull-up circuit;

wherein the calibration circuit is configured to generate a current in the replica of the pull-down circuit and to apply a first impedance control signal to the pull-down circuit and to the replica of the pull-down circuit based on a voltage generated at the replica of the pull-down circuit in response to the current in the replica of the pull-down circuit; and

wherein the calibration circuit is further configured to generate a current in the replica of the pull-up circuit and to apply a second impedance control signal to the pull-up circuit and to the replica of the pull-up circuit based on a voltage generated at the replica of the pull-up circuit in response to the current in the replica of the pull-up circuit.

6. An impedance adjustment circuit according to claim 5, wherein the pull-up circuit and the pull-down circuit are included in an output driver and/or an on-die terminator (ODT).

7. An impedance adjustment circuit according to claim 6, wherein the calibration circuit comprises:

a first current mirror configured to match the current in the reference resistor and the current in the replica of the pull-down circuit;

a first impedance control signal generator configured to generate the first impedance control signal responsive to the voltage of the replica of the pull-down circuit so as to substantially equalize the voltage of the replica of the pull-down circuit and a first reference voltage;

a second current mirror configured to match the current in the reference resistor and the current in the replica of the pull-up circuit; and

a second impedance control signal generator configured to generate the second impedance control signal responsive to the voltage of the replica of the pull-up circuit so as to substantially equalize a voltage across the replica of the pull-up circuit and a second reference voltage.

8. An impedance adjustment circuit according to claim 7:

wherein the first impedance control signal generator comprises;

a first comparator configured to generate a first comparison signal responsive to a comparison of the voltage of the replica of the pull-down circuit to the first reference voltage; and

a first register configured to increment and/or decrement the first impedance control signal responsive to the first comparison signal; and

wherein the second impedance control signal generator comprises;

a second comparator configured to generate a second comparison signal responsive to a comparison of the voltage of the replica of the pull-up circuit to the second reference voltage; and

a second register configured to increment and/or decrement the second impedance control signal responsive to the second comparison signal.

9. An impedance adjustment circuit according to claim 7, wherein the first reference voltage comprises a first one of a logic high reference voltage and a logic low reference voltage and wherein the second reference voltage comprises a second one of the logic high reference voltage and the logic low reference voltage.

10. An impedance adjustment circuit according to claim 9, wherein the pull-down circuit and the pull-up circuit are included in an output driver, wherein the first reference voltage comprises the logic low reference voltage, and wherein the second reference voltage comprises the logic high reference voltage.

11. An impedance adjustment circuit according to claim 9, wherein the pull-down circuit and the pull-up circuit are included in an ODT, wherein the first reference voltage comprises the logic high reference voltage, and wherein the second reference voltage comprises the logic low reference voltage.

12. An impedance adjustment circuit according to claim 2, wherein the calibration circuit comprises:

a current mirror configured to match a current in the reference resistor and the current in the replica of the variable impedance circuit; and

an impedance control signal generator configured to generate the impedance control signal responsive to the voltage of the replica of the variable impedance circuit so as to substantially equalize the voltage of the replica of the variable impedance circuit and a reference voltage.

13. An impedance adjustment circuit according to claim 12, wherein the impedance control signal generator comprises:

a comparator configured to generate a comparison signal responsive to a comparison of the voltage of the replica of the variable impedance circuit and the reference voltage; and

a register configured to increment and/or decrement the impedance control signal responsive to the comparison signal.

14. An impedance adjustment circuit according to claim 12, wherein the comparator comprises a first comparator, and wherein the current mirror comprises:

a first current source configured to generate the current in the reference resistor responsive to a current control signal;

a second current source configured to generate the current in the replica of the variable impedance circuit responsive to the current control signal; and

a second comparator configured to generate the current control signal responsive to a comparison of the reference voltage and a voltage generated at the reference resistor responsive to the current in the reference resistor.

15. An impedance adjustment circuit according to claim 12, wherein the comparator comprises a first comparator, wherein the reference voltage comprises a first reference voltage, and wherein the current mirror comprises:

a first current source configured to generate the current in the reference resistor responsive to a current control signal;

a second current source configured to generate the current in the replica of the variable impedance circuit responsive to the current control signal; and

a second comparator configured to generate the current control signal responsive to a comparison of a second reference voltage and a voltage generated at the reference resistor responsive to the current in the reference resistor.

16. An impedance adjustment circuit according to claim 2, wherein each of the variable impedance circuit and the replica of the variable impedance circuit comprises a plurality of resistors configured to be selectively coupled in parallel responsive to the impedance control signal.

17. An impedance adjustment circuit according to claim 2, wherein the calibration circuit is included in an integrated circuit device configured to be coupled to the reference resistor at an external terminal of the integrated circuit device.

18. An integrated circuit including an impedance adjustment circuit according to claim 1 in combination with the variable impedance circuit, wherein the variable impedance circuit comprises a pull-down circuit and/or a pull-up circuit coupled to an external signal node of the integrated circuit.

19. An integrated circuit device comprising:

a variable impedance pull-down circuit and a variable impedance pull-up circuit coupled to an external signal node;

a first calibration circuit configured to generate respective first and second impedance control signals for the variable impedance pull-down and pull-up circuits;

a second calibration circuit configured to generate respective third and fourth impedance control signals for the variable impedance pull-down and pull-up circuits; and

a selection circuit configured to receive the first, second, third and fourth impedance control signals, to apply the first and third impedance control signals to the respective variable impedance pull-up and pull-down circuits in response to a first state of a selection control signal, and to apply the second and fourth impedance control signals to the respective variable impedance pull-up and pull-down circuits in response to a second state of the selection control signal.

20. An integrated circuit device according to claim 19, wherein the first state of the selection control signal corresponds to operation of the variable impedance pull-down and pull-up circuits as an output driver, and wherein the second state of the selection control signal corresponds to operation of the variable impedance pull-down and pull-up circuits as an ODT.

21. An integrated circuit device according to claim 19:

wherein the first calibration circuit comprises a first replica of the pull-down circuit and a first replica of the pull-up circuit and is configured to generate respective ones of the first and second impedance control signals based on respective voltages generated at respective ones of the first replica of the pull-down circuit and the first replica of the pull-up circuit in response to a first reference current; and

wherein the second calibration circuit comprises a second replica of the pull-down circuit and a second replica of the pull-up circuit and is configured to generate respective ones of the third and fourth impedance control signals based on respective voltages generated at respective ones of the second replica of the pull-down circuit and the second replica of the pull-up circuit in response to a second reference current.

22. An integrated circuit device according to claim 21, wherein the first and second calibration circuits are configured to generate the first and second reference currents based on respective first and second reference resistors coupled thereto.

23. An integrated circuit device according to claim 22:

wherein the first calibration circuit is configured to match a current in the first replica of the pull-down circuit and a current in the first reference resistor and to generate the first impedance control signal based on a voltage generated at the first replica of the pull-down circuit in response to the current in the first replica of the pull-down circuit;

wherein the first calibration circuit is further configured to match a current in the first replica of the pull-up circuit and the current in the first reference resistor and to generate the second impedance control signal based on a voltage generated at the first replica of the pull-up circuit in response to the current in the first replica of the pull-up circuit;

wherein the second calibration circuit is configured to match a current in the second replica of the pull-down circuit and a current in the second reference resistor and to generate the third impedance control signal based on a voltage generated at the second replica of the pull-down circuit in response to the current in the second replica of the pull-down circuit; and

wherein the second calibration circuit is further configured to match a current in the second replica of the pull-up circuit and the current in the second reference resistor and to generate the fourth impedance control signal based on a voltage generated at the second replica of the pull-up circuit in response to the current in the second replica of the pull-up circuit.

24. An integrated circuit device according to claim 19:

wherein the first calibration circuit comprises;

a first register configured to store the first impedance control signal; and

a first inverter configured to receive the stored first impedance control signal and to invert the stored first impedance control signal to generate the second impedance control signal; and

wherein the second calibration circuit comprises;

a second register configured to store the third impedance control signal; and

a second inverter configured to receive the stored third impedance control signal and to invert the stored third impedance control signal to generate the fourth impedance control signal.

25. A method of controlling an impedance of a variable impedance circuit, the method comprising:

generating a voltage at a replica of the variable impedance circuit in response to a reference current; and

generating an impedance control signal for the variable impedance circuit based on the voltage at the replica of the variable impedance circuit.

26. A method according to claim 25, further comprising generating the reference current based on a reference resistor.

27. A method according to claim 26, wherein generating a voltage at a replica of the variable impedance circuit in response to a reference current comprises matching a current in the replica of the variable impedance circuit to a current in the reference resistor to thereby generate the voltage at the replica of the variable impedance circuit.

28. A method according to claim 25, wherein the variable impedance circuit comprises a pull-down circuit and a pull-up circuit coupled to an external signal node of an integrated circuit device, wherein the replica of the variable impedance circuit comprises a replica of the pull-down circuit and a replica of the pull-up circuit, and wherein the method comprises:

generating a current in the replica of the pull-down circuit;

applying a first impedance control signal to the pull-down circuit and the replica of the pull-down circuit based on a voltage generated at the replica of the pull-down circuit in response to a current in the replica of the pull-down circuit;

generating a current in the replica of the pull-up circuit; and

applying a second impedance control signal to the pull-up circuit and the replica of the pull-up circuit based on a voltage generated at the replica of the pull-up circuit in response to a current in the replica of the pull-up circuit.

29. A method according to claim 28, wherein the pull-up circuit and the pull-down circuit are included in an output driver and/or an on-die terminator (ODT).

30. A method according to claim 28, comprising:

matching the current in the reference resistor and the current in the replica of the pull-down circuit;

generating the first impedance control signal responsive to the voltage of the replica of the pull-down circuit so as to substantially equalize the voltage of the replica of the pull-down circuit and a first reference voltage;

matching the current in the reference resistor and the current in the replica of the pull-up circuit; and

generating the second impedance control signal responsive to the voltage of the replica of the pull-up circuit so as to substantially equalize a voltage across the replica of the pull-up circuit and a second reference voltage.

31. A method according to claim 30, wherein the first reference voltage comprises a first one of a logic high reference voltage and a logic low reference voltage and wherein the second reference voltage comprises a second one of the logic high reference voltage and the logic low reference voltage.

32. A method according to claim 31, wherein the pull-down circuit and the pull-up circuit are included in an output driver, wherein first reference voltage comprises the logic low reference voltage, and wherein the second reference voltage comprises the logic high reference voltage.

33. A method according to claim 31, wherein the pull-down circuit and the pull-up circuit are included in an ODT, wherein the first reference voltage comprises the logic high reference voltage, and wherein the second reference voltage comprises the logic low reference voltage.