Method of fabricating poly crystalline silicon TFT

• US 20060088961A1
• Filed: 10/12/2005
• Published: 04/27/2006
• Est. Priority Date: 10/12/2004
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Ji-sim, Kwon, Jang-yeon, Noguchi, Takashi, Kim, Do-young
• Application Number:
  US11/247,134
• Publication Number:
  US 20060088961A1
• Time in Patent Office: Days
• US Class Current: 438/149
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

A method of fabricating a poly crystalline silicon thin film transistor (TFT) is provided. The method includes the operations of forming a poly crystalline silicon having a source, a drain, and a channel region between the source and the drain on a substrate in a predetermined pattern; forming an insulating layer on the poly crystalline silicon; forming a silicon-based heat absorption material layer on the insulating layer; exposing the source and the drain by patterning the insulating layer and the heat absorption material layer and forming a gate and a gate insulating layer corresponding to the channel region; injecting impurities into the source, the drain, and the gate; and heat processing the gate insulating layer and the heat absorption material layer by applying thermal energy to the heat absorption material layer. In the heat treatment, the gate material absorbs some of the heat and passes the remaining heat. The heat treatment of the gate insulating layer under the gate can be performed efficiently.

Claims

1. A method of fabricating a thin film transistor comprising the operations of:

forming a poly crystalline silicon having a source, a drain, and a channel region between the source and the drain on a substrate in a predetermined pattern;

forming an insulating layer on the poly crystalline silicon;

forming a silicon-based heat absorption material layer on the insulating layer;

exposing the source and the drain by patterning the insulating layer and the heat absorption material layer and forming a gate and a gate insulating layer corresponding to the channel region;

injecting impurities into the source, the drain, and the gate; and

heat processing the gate insulating layer and the heat absorption material layer by applying thermal energy to the heat absorption material layer.

2. The method of claim 1, wherein the forming of the insulating layer on the poly crystalline silicon and the forming of the silicon-based heat absorption material layer on the insulating layer are performed sequentially in the same chamber.

3. The method of claim 2, wherein a gate insulating layer and the heat absorption material layer are continuously formed in an inductively coupled plasma chemical vapor depositon (ICP-CVD) method.

4. The method of claim 1, wherein the forming of the poly crystalline silicon includes the operations of:

depositing amorphous silicon on the substrate;

polycrystallizing the amorphous silicon through heat treatment; and

patterning the poly crystallized silicon.

5. The method of claim 4, wherein the poly crystallization process is performed in an excimer laser annealing (ELA) method.

6. The method of claim 4, wherein the heat treatment of the amorphous silicon layer on the substrate is performed in the ELA method.