Layer fill for homogenous technology processing

• US 20060091423A1
• Filed: 10/29/2004
• Published: 05/04/2006
• Est. Priority Date: 10/29/2004
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Poechmueller, Peter
• Application Number:
  US10/977,644
• Publication Number:
  US 20060091423A1
• Time in Patent Office: Days
• US Class Current: 257/206
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out

Abstract

Spare transistors are formed in regions of a semiconductor device where functional transistors are not formed, providing uniformity in etch and polishing processes, and resulting in transistors with more uniform parameters on the semiconductor device. The spare transistors may not be electrically connected to other components on the device, or alternatively, the spare transistors may be connected to other components for use as spare transistors, for example. The gates of the spare transistors provide a homogeneous gate material layer, resulting in improved etch, polishing, and lithography processes for the semiconductor device.

Claims

1. A semiconductor device, comprising:

a workpiece, the workpiece comprising a first region and a second region;

a plurality of first transistors disposed in the first region of the workpiece, the plurality of first transistors comprising functioning devices, at least a portion of one of the first transistors having a width comprising a first dimension; and

a plurality of second transistors disposed in the second region of the workpiece, the plurality of second transistors comprising non-functioning devices, wherein each of the plurality of second transistors is spaced apart from a first transistor by a second dimension, wherein the second dimension comprises about five times the first dimension or less.

2. The semiconductor device according to claim 1, wherein the semiconductor device comprises a ground connection and a power supply connection, wherein each of the plurality of second transistors is coupled to the ground connection and the power supply connection of the semiconductor device.

3. The semiconductor device according to claim 1, wherein the second dimension comprises about two times the first dimension or less.

4. The semiconductor device according to claim 1, wherein the first dimension comprises a minimum feature size of the semiconductor device.

5. The semiconductor device according to claim 4, wherein each of the plurality of first transistors comprises a first gate, wherein the first gates comprise the minimum feature size, and wherein each of the plurality of second transistors comprises a second gate, the second gate comprising the minimum feature size.

6. The semiconductor device according to claim 5, wherein a portion of at least one of the second gate extends into the first region proximate a first gate.

7. A semiconductor device, comprising:

a plurality of functional transistor gates formed in a first region of a workpiece, each of the plurality of functional transistor gates having a width comprising a first dimension; and

at least one non-functional transistor gate formed in a second region of the workpiece proximate the first region, the at least one non-functional transistor gate having a width comprising substantially the first dimension, wherein the non-functional transistor gate is disposed apart from the functional transistor gates by a dimension equal to or less than about five times the first dimension.

8. The semiconductor device according to claim 7, wherein the non-functional transistor gate is disposed apart from the functional transistor gates by a dimension equal to or less than about two times the first dimension.

9. The semiconductor device according to claim 7, wherein the semiconductor device comprises a ground connection and a power supply connection, wherein the at least one non-functional transistor gate comprises a gate of a non-functional transistor, wherein each at least one non-functional transistor is coupled to the ground connection and the power supply connection of the semiconductor device.

10. The semiconductor device according to claim 7, wherein the first dimension comprises a minimum feature size of the semiconductor device.

11. The semiconductor device according to claim 7, wherein a portion of at least one non-functional transistor gate extends into the first region proximate a functional transistor gate.

12. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece, the workpiece comprising a first region and a second region;

forming a plurality of first transistors in the first region of the workpiece, the plurality of first transistors comprising functioning devices, at least a portion of one of the first transistors having a width comprising a first dimension; and

forming a plurality of second transistors in the second region of the workpiece, the plurality of second transistors comprising non-functioning devices, wherein each of the plurality of second transistors is spaced apart from a first transistor by a second dimension, wherein the second dimension comprises about five times the first dimension or less.

13. The method according to claim 12, wherein the first dimension comprises a minimum feature size of the semiconductor device.

14. The method according to claim 12, wherein forming the plurality of second transistors comprises forming the second transistors such that the second dimension comprises about two times the first dimension or less.

15. The method according to claim 12, further comprising forming a ground connection and a power supply connection, and connecting each of the plurality of second transistors to the ground connection and the power supply connection of the semiconductor device.

16. The method according to claim 12, wherein forming each of the plurality of first transistors comprises forming the plurality of first transistors comprising a first gate, the first gate comprising a width comprising the first dimension, wherein forming each of the plurality of second transistors comprises forming a second gate, the second gate comprising the first dimension.

17. The method according to claim 16, wherein the first dimension comprises a minimum feature size of the semiconductor device.

18. The method according to claim 16, wherein forming the plurality of first transistors and forming the plurality of second transistors comprises depositing a gate material, and patterning the gate material using a single lithography mask.

19. The method according to claim 18, wherein forming the plurality of first transistors and forming the plurality of second transistors comprises etching the gate material, wherein the second gates of the plurality of second transistors causes the formation of the first gates of the plurality of first transistors to have substantially uniform dimensions.

20. The method according to claim 19, wherein forming the plurality of second transistors comprises extending the second gates into the first region proximate the first gates.

21. The method according to claim 12, wherein forming the plurality of first transistors in the first region of the workpiece and forming the plurality of second transistors in second region of the workpiece comprises:

implanting the workpiece with a first impurity;

forming a gate oxide material over the workpiece;

forming a gate material over the gate oxide material;

patterning the gate material; and

implanting exposed portions of the workpiece with a second impurity, the second impurity being different from the first impurity.

22. The method according to claim 21, wherein depositing the gate material comprises forming polysilicon, a metal, a silicide, a hard mask, an etch stop material, or combinations thereof.

23. A method of designing a semiconductor device, the method comprising:

determining a layout for a plurality of functional transistors, each of the plurality of functional transistors having at least one first gate, the layout having regions with no first gates disposed therein, each at least one first gate comprising a width comprising a first dimension; and

determining a layout for a plurality of non-functional transistors in the regions with no first gates disposed therein, each of the plurality of non-functional transistors comprising at least one second gate having substantially the same dimensions as the at least one first gate and being spaced apart from the plurality of functional transistors by a second dimension, the second dimension comprising about five times the first dimension or less.

24. The method according to claim 23, further comprising:

coupling each of the plurality of non-functional transistors to a ground connection and a power supply connection of the semiconductor device.

25. The method according to claim 23, further comprising:

fabricating the semiconductor device;

testing the plurality of functional transistors; and

connecting at least one of the plurality of non-functional transistors to function as a functional transistor.

26. The method according to claim 25, wherein connecting at least one of the plurality of non-functional transistors to function as a functional transistor comprises changing a lithography mask for a metallization layer for a conductive line layer of the semiconductor device, to connect a conductive line to the at least one non-functional transistor.

27. The method according to claim 26, wherein connecting at least one of the plurality of non-functional transistors to function as a functional transistor further comprises changing a lithography mask for a metallization layer for a via layer of the semiconductor device, to connect a via to the at least one non-functional transistor.