Semiconductor device and method of producing a semiconductor device

• US 20060091424A1
• Filed: 10/29/2004
• Published: 05/04/2006
• Est. Priority Date: 10/29/2004
• Status: Active Grant

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Riedel, Stephan, Strassburg, Matthias
• Granted Patent: US 7,238,974 B2
• Time in Patent Office: Days
• US Class Current: 257/208
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Semiconductor Device And Method Of Producing A Semiconductor Device A semiconductor device comprises a memory cell (160) including a transistor body (150) having a top surface (111) and including a first doping area (10a) and a second doping area (10b) with a channel region (110) in between. The memory cell (160) further includes a gate electrode (3a) arranged above the channel region (110) and separated therefrom by a dielectric layer (2a). An oxide-nitride-oxide layer (66) has first portions (661) and second portions (662). The first portions (661) of the oxide-nitride-oxide layer (66) are arranged above at least parts of the first and second doping areas (10a, 10b) and are substantially parallel to the top surface (111) of the transistor body (150). The second portions (662) of the oxide-nitride-oxide layer (66) are adjacent to the gate electrode (3a) and extend in a direction not substantially parallel to the top surface (111) of the transistor body (150).

Claims

1. A semiconductor device comprising:

a transistor body having a top surface and having a first doping area and a second doping area, and a channel region between the first doping area and the second doping area;

a gate dielectric located over the top surface of the transistor body;

a gate electrode disposed above the channel region and disposed on the gate dielectric such that the gate dielectric is located between the gate electrode and the top surface of the transistor body; and

an oxide-nitride-oxide layer having first portions, each having a bottom surface and second portions, each having a bottom surface;

wherein the first portions of the oxide-nitride-oxide layer are disposed above the first and second doping areas and the bottom surfaces of the first portions of the oxide-nitride-oxide layer are substantially parallel to the top surface of the transistor body; and

wherein the bottom surfaces of the second portions of the oxide-nitride-oxide layer are located adjacent to the gate electrode and extend in a direction not substantially parallel to the top surface of the transistor body.

2. The semiconductor device according to claim 1, wherein the second portions of the oxide-nitride-oxide layer extend substantially orthogonal with respect to the first portions of the oxide-nitride-oxide layer.

3. The semiconductor device according to claim 1, wherein the bottom surfaces of the first portions of the oxide-nitride-oxide layer are in contact with the top surface of the transistor body, the bottom surfaces of the second portions of the oxide-nitride-oxide layer are in contact with sidewalls of the gate electrode.

4. The semiconductor device according to claim 1, wherein the gate electrode comprises polysilicon.

5. The semiconductor device according to claim 1, wherein the gate dielectric layer comprises one of silicon dioxide or silicon oxide.

6. The semiconductor device according to claim 1, wherein the channel region is doped with a dopant comprising either boron and/or indium, and wherein the first and second doping areas are doped with arsenic.

7. The semiconductor device according to claim 1, further comprising a plurality of memory cells, the memory cells being arranged in a matrix having columns and rows, the rows aligned to a first direction, the columns aligned to a second direction, the second direction orthogonal with respect to the first direction.

8. The semiconductor device according to claim 7, wherein a subset of the first and second doping areas of the plurality of the memory cells arranged in the same one of rows is aligned with a line parallel to the first direction.

9. The semiconductor device according to claim 7, wherein the second portions of the oxide-nitride-oxide layer extend substantially orthogonal with respect to the first portions of the oxide-nitride-oxide layer.

10. The semiconductor device according to claim 7, wherein the bottom surfaces of the first portions of the oxide-nitride-oxide layer are in contact with the top surface of the transistor body, and the bottom surfaces of the second portions of the oxide-nitride-oxide layer are in contact with sidewalls of the gate electrode.

11. The semiconductor device according to claim 7, wherein the gate electrode comprises polysilicon.

12. The semiconductor device according to claim 7, wherein the dielectric layer comprises one of silicon dioxide or silicon oxide.

13. The semiconductor device according to claim 7, wherein the channel region is doped with a dopant, said dopant comprising one of boron and/or indium, and wherein the first and second doping areas are doped with arsenic.

14. The semiconductor device according to claim 7, further comprising a nitride spacer, the nitride spacer arranged vertical with respect to the top surface of the transistor body, the nitride spacer located on the sidewalls of the gate electrode.

15. The semiconductor device according to claim 7, further comprising dopants having anti-punch characteristics disposed between adjacent rows of gate electrodes and extending parallel to the first direction, the dopants being located beneath the top surface of the transistor body.

16. The semiconductor device according to claim 7, further comprising a bitline disposed parallel to the second direction, the bitline electrically coupling at least two adjacent doping areas located parallel to the second direction.

17. The semiconductor device according to claim 16, further comprising an oxide line disposed on the bitline, the oxide line disposed between the first portions of the oxide-nitride-oxide layer.

18. The semiconductor device according to claim 7, further comprising a wordline, the wordline electrically connected to at least two of a multitude of gate electrodes arranged in a same one of the rows.

19. The semiconductor device according to claim 18, wherein the wordline comprises one or more materials selected from the group consisting of polysilicon, metal and metal silicide.

20. The semiconductor device according to claim 19 wherein the wordline comprises tungsten silicide.

21. A semiconductor device, comprising:

a substrate having a top surface;

a multitude of gate electrodes disposed on the top surface of the substrate, the gate electrodes disposed in an array having rows located parallel to a first direction and columns located parallel to a second direction, which is orthogonal with respect to the first direction;

a multitude of gate dielectrics, one of the multitude of the gate dielectrics disposed between one of the multitude of gate electrodes and the top surface of the substrate;

at least two bitlines disposed along the second direction on either side of a column of the gate electrodes, the bitlines buried beneath the top surface of the substrate;

a channel region disposed in the substrate between the bitlines and beneath one of the gate electrodes; and

an oxide-nitride-oxide layer having first portions each having a bottom surface, and second portions each having a bottom surface;

wherein the first portions of the oxide-nitride-oxide layer are disposed above the first and second doping areas, and the bottom surfaces of the first portions of the oxide-nitride-oxide layer are substantially parallel to the top surface of the substrate; and

wherein the bottom surfaces of the second portions of the oxide-nitride-oxide layer are located adjacent to the gate electrode and extend in a direction not substantially parallel to the top surface of the substrate.

22. The semiconductor device according to claim 21, wherein the second portions of the oxide-nitride-oxide layer extend substantially orthogonal with respect to the first portions of the oxide-nitride-oxide layer.

23. The semiconductor device according to claim 21, wherein the bottom surfaces of the first portions of the oxide-nitride-oxide layer are in contact with the top surface of the substrate, and the bottom surfaces of the second portions of the oxide-nitride-oxide layer are in contact with sidewalls of the gate electrode.

24. The semiconductor device according to claim 21, wherein the gate electrodes comprise polysilicon.

25. The semiconductor device according to claim 21, wherein the gate dielectric comprises one of silicon dioxide or silicon oxide.

26. The semiconductor device according to claim 21, wherein the channel region is doped with boron and/or indium;

and wherein the first and second doping areas are doped with arsenic.

27. The semiconductor device according to claim 21, further comprising a nitride spacer, the nitride spacer arranged vertical with respect to the top surface of the substrate, the nitride spacer located on sidewalls of the gate electrode.

28. The semiconductor device according to claim 21, further comprising dopants having anti-punch characteristics disposed between adjacent rows of gate electrodes and extending parallel to the first direction, the dopants located beneath the top surface of the substrate.

29. The semiconductor device according to claim 21, further comprising at least two oxide lines, each disposed on one of the bitlines, each oxide line disposed between the first portions of the oxide-nitride-oxide layer.

30. The semiconductor device according to claim 21, further comprising a wordline that is electrically connected to at least two of the multitude of gate electrodes arranged in a same one of the rows.

31. The semiconductor device according to claim 30, wherein the wordline comprises one or more materials selected from the group consisting of polysilicon, metal and metal silicide.

32. A method of producing a semiconductor device, the method comprising:

providing a semiconductor substrate having a top surface;

depositing an oxide layer on the substrate;

introducing dopants into the substrate to form a well;

depositing a conductive layer onto the oxide layer;

partially etching the conductive layer and the oxide layer to form a gate island thereby exposing the top surface of the semiconductor substrate; and

depositing an oxide-nitride-oxide layer onto the exposed top surface of the semiconductor substrate and the top surface and sidewalls of the gate island.

33. The method according to claim 32, wherein depositing a conductive layer comprises depositing a polysilicon layer.

34. The method according to claim 32, wherein the step of introducing the dopants is performed before the step of depositing the oxide layer.

35. The method according to claim 32, further comprising introducing dopants into the substrate to form a doped region located between the gate island and adjacent a second gate island, the gate island and the second gate island aligned along a second direction.

36. The method according to claim 35, wherein the dopant has anti-punch characteristics.

37. The method according to claim 32 further comprising:

depositing a nitride layer onto the oxide-nitride-oxide layer to form horizontal and vertical portions of the nitride layer; and

etching horizontal portions of the nitride layer and the oxide-nitride-oxide layer located beneath the nitride layer to form a nitride spacer.

38. The method according to claim 37, further comprising introducing dopants on either side of the gate island to form a first doping area and a second doping area.

39. The method according to claim 36, wherein introducing dopants to form the well comprises introducing one of boron and/or indium dopants, and wherein introducing dopants to form the first doping area and the second doping area comprises introducing arsenic dopants.

40. The method according to claim 37, wherein multiple gate islands are arranged along a row and multiple gate islands are arranged along a column;

the rows being arranged parallel to a first direction and the columns being arranged parallel to a second direction orthogonal with respect to the first direction.

41. The method according to claim 40, wherein the step of etching horizontal portions of the nitride layer is used to form a gap, the gap being located parallel to the second direction between adjacent columns of gate islands.

42. The method according to claim 41, comprising a step of introducing dopants through the gap into the well to form a bitline.

43. The method according to claim 42, further comprising forming an oxide line in the gap on the bitline.

44. The method according to claim 43, further comprising forming a wordline, the wordline being electrically connected to at least two of the multitude of gate islands arranged in a same one of the rows.

45. The method according to claim 44, wherein the wordline comprises one or more materials selected from the group consisting of polysilicon, metal and metal silicide.

46. The method according to claim 45, wherein forming a wordline comprises depositing polysilicon and forming a silicide over the polysilicon.

47. The method according to claim 46, wherein forming a wordline comprises forming a wordline comprising tungsten silicide.