Metal-semiconductor field effect transistors (MESFETs) having drains coupled to the substrate and methods of fabricating the same

• US 20060091430A1
• Filed: 10/29/2004
• Published: 05/04/2006
• Est. Priority Date: 10/29/2004
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Allen, Scott, Sriram, Saptharishi
• Granted Patent: US 7,348,612 B2
• Time in Patent Office: Days
• US Class Current: 257/280
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/66848 with a Schottky gate, i.e. MESFET
• CPC Class Codes: H01L 29/8128 with recessed gate

Abstract

The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a MESFET having a source region, a drain region and a gate contact. The gate contact is disposed between the source region and the drain region. The drain region is electrically coupled to the substrate through a contact via hole to the substrate. Related methods of fabricating MESFETs are also provided herein.

Claims

1. A unit cell of a metal-semiconductor field-effect transistor (MESFET), comprising a MESFET on a substrate, the MESFET having a source region, a drain region and a gate contact, the gate contact being between the source region and the drain region and the drain region being electrically coupled to the substrate through a contact via hole to the substrate.

2. The unit cell of claim 1, wherein the substrate comprises an n-type substrate and wherein the contact via hole extends through the drain region and exposes a first surface of the substrate.

3. The unit cell of claim 2, wherein the substrate comprises an n-type silicon carbide (SiC) substrate.

4. The unit cell of claim 2, further comprising first and second ohmic contacts on the source and drain regions that respectively define a source contact and a drain contact, wherein the contact via hole extends through at least a portion of the drain contact.

5. The unit cell of claim 4, further comprising:

a substrate contact on the exposed first surface of the substrate; and

a first overlayer in the contact via hole and extending to the drain contact and the substrate contact, the first overlayer electrically coupling the drain contact to the substrate contact to electrically couple the drain region to the substrate.

6. The unit cell of claim 5, wherein the substrate contact is a non-ohmic contact.

7. The unit cell of claim 5, further comprising a third ohmic contact on a second surface of the substrate, opposite the first surface of the substrate, that defines a backside substrate contact.

8. The unit cell of claim 5, wherein the drain region is electrically coupled to a drain pad and wherein the contact via hole is at least partially located in the drain pad.

9. The unit cell of claim 5, wherein the substrate contact comprise an ohmic contact, the unit cell further comprising:

a non-ohmic backside substrate contact on a second surface of the substrate, opposite the first surface of the substrate;

a drain pad electrically coupled to the drain region; and

a wire electrically coupling the drain pad to the backside substrate contact.

10. The unit cell of claim 1, wherein the substrate comprises a semi-insulating substrate or an n-type substrate and wherein the contact via hole extends through a first surface of the substrate to a second surface of the substrate, opposite the first surface of the substrate.

11. The unit cell of claim 10, wherein the substrate comprises an n-type silicon carbide (SiC) substrate or a semi-insulating SiC substrate.

12. The unit cell of claim 10, further comprising:

first and second ohmic contacts on the source region and the drain region, respectively, that respectively define a source contact and a drain contact; and

a backside substrate contact on the second surface of the substrate, wherein the contact via hole exposes a portion of the backside substrate contact.

13. The unit cell of claim 12, further comprising:

a first overlayer in the contact via hole and extending to the drain contact and the backside substrate contact, the first overlayer electrically coupling the drain contact to the backside substrate contact to electrically couple the drain region to the substrate.

14. The unit cell of claim 12, wherein the drain region is electrically coupled to a drain pad and wherein the contact via hole is at least partially disposed in the drain pad.

15. The unit cell of claim 1, wherein the substrate has a thickness of from about 100 μ

m to about 400 μ

m.

16. The unit cell of claim 15, wherein the thickness of the substrate is about 300 μ

m.

17. The unit cell of claim 1, further comprising an n-type conductivity channel layer on the substrate, the gate contact being disposed on the n-type conductivity layer.

18. The unit cell of claim 17, wherein the n-type conductivity channel layer comprises n-type conductivity silicon carbide (SiC) and wherein the gate extends into the n-type conductivity SiC channel layer.

19. The unit cell of claim 18, wherein the gate contact is disposed in a single recess.

20. The unit cell of claim 18, wherein the gate contact is disposed in a double recess.

21. The unit cell of claim 17, wherein the contact via hole comprises a first contact via hole, the unit cell further comprising:

a p-type conductivity region beneath the source region and having an end that extends towards the drain region, the p-type conductivity region being spaced apart from the n-type conductivity channel layer and being electrically coupled to the source region; and

a second contact via hole adjacent the source region that exposes the p-type conductivity region; and

an ohmic contact on the exposed portion of the p-type conductivity region.

22. The unit cell of claim 17, further comprising implanted n-type conductivity regions in the n-type conductivity channel layer that respectively define the source region and the drain region, the implanted n-type conductivity regions having carrier concentrations greater than a carrier concentration of the n-type conductivity channel layer, wherein first and second ohmic contacts that respectively define a source contact and a drain contact are disposed on the source region and the drain region, respectively.

23. The unit cell of claim 17 further comprising:

a first buffer layer on the substrate; and

a second buffer layer on the first buffer layer, wherein the n-type conductivity channel layer is on the second buffer layer and wherein the contact via hole extends through the drain region, the n-type channel region and the first and second buffer layers to a first surface of the substrate.

24. The unit cell of claim 23 wherein the contact via hole further extends through the first surface of the substrate to a second surface of the substrate, opposite the first surface of the substrate.

25. The unit cell of claim 17 wherein the n-type conductivity channel layer comprises a first n-type conductivity channel layer on the substrate and a second n-type conductivity channel layer on the first n-type conductivity channel layer.

26. The unit cell of claim 17 wherein the n-type conductivity channel layer comprises first, second and third n-type conductivity SiC channel layers and wherein the first, second and third n-type conductivity channel layers have respective first, second and third carrier concentrations.

27. The unit cell of claim 1, wherein the substrate comprises n-type conductivity gallium arsenide (GaAs), semi-insulating GaAs, n-type conductivity gallium nitride (GaN) or semi-insulating GaN.

28. A unit cell of a metal-semiconductor field-effect transistor (MESFET), comprising:

a silicon carbide (SiC) MESFET having a source region, a drain region and a gate contact, the gate contact being between the source region and the drain region; and

first and second ohmic contacts on the source region and the drain region. respectively, that respectively define a source contact and a drain contact, the drain region being electrically coupled to the substrate through a contact via hole to the substrate.

29. The unit cell of claim 28, wherein the substrate comprises an n-type substrate and wherein the contact via hole extends through the drain region and exposes a first surface of the substrate.

30. The unit cell of claim 29, further comprising first and second ohmic contacts on the source and drain regions that respectively define a source contact and a drain contact, wherein the contact via hole extends through at least a portion of the drain contact.

31. The unit cell of claim 30, further comprising:

a substrate contact on the exposed first surface of the substrate; and

a first overlayer in the contact via hole and extending to the drain contact and the substrate contact, the first overlayer electrically coupling the drain contact to the substrate contact to electrically couple the drain region to the substrate.

32. The unit cell of claim 31, wherein the substrate contact is a non-ohmic contact.

33. The unit cell of claim 31, further comprising a third ohmic contact on a second surface of the substrate, opposite the first surface of the substrate, that defines a backside substrate contact.

34. The unit cell of claim 31, wherein the drain region is electrically coupled to a drain pad and wherein the contact via hole is at least partially located in the drain pad.

35. The unit cell of claim 31, wherein the substrate contact comprises an ohmic contact, the unit cell further comprising:

a non-ohmic backside substrate contact on a second surface of the substrate, opposite the first surface of the substrate;

a drain pad electrically coupled to the drain region; and

a wire electrically coupling the drain pad to the backside substrate contact.

36. The unit cell of claim 28, wherein the substrate comprises a semi-insulating substrate or an n-type substrate and wherein the contact via hole extends through a first surface of the substrate to a second surface of the substrate, opposite the first surface of the substrate.

37. The unit cell of claim 36, further comprising:

first and second ohmic contacts on the source region and the drain region, respectively, that respectively define a source contact and a drain contact; and

a backside substrate contact on the second surface of the substrate, wherein the contact via hole exposes a portion of the backside substrate contact.

38. The unit cell of claim 37, further comprising:

a first overlayer in the contact via hole and extending to the drain contact and the backside substrate contact, the first overlayer electrically coupling the drain contact to the backside substrate contact to electrically couple the drain region to the substrate.

39. The unit cell of claim 37, wherein the drain region is electrically coupled to a drain pad and wherein the contact via hole is at least partially disposed in the drain pad.

40. A method of forming a unit cell of a metal-semiconductor field-effect transistor (MESFET), comprising forming a MESFET on a substrate, the MESFET having a source region, a drain region and a gate contact, the gate contact being between the source region and the drain region and the drain region being electrically coupled to the substrate through a contact via hole to the substrate.

41. The method of claim 40, wherein the substrate comprises an n-type substrate and wherein the contact via hole extends through the drain region and exposes a first surface of the substrate.

42. The method of claim 41, wherein the substrate comprises an n-type silicon carbide (SiC) substrate.

43. The method of claim 41, further comprising forming first and second ohmic contacts on the source and drain regions that respectively define a source contact and a drain contact, wherein the contact via hole extends through at least a portion of the drain contact.

44. The method of claim 43, further comprising:

forming a substrate contact on the exposed first surface of the substrate; and

forming a first overlayer in the contact via hole and extending to the drain contact and the substrate contact, the first overlayer electrically coupling the drain contact to the substrate contact to electrically couple the drain region to the substrate.

45. The method of claim 44, wherein the substrate contact is a non-ohmic contact.

46. The method of claim 44 further comprising forming a third ohmic contact on a second surface of the substrate, opposite the first surface of the substrate, that defines a backside substrate contact.

47. The method of claim 44, further comprising electrically coupling the drain region to a drain pad, wherein the contact via hole is at least partially located in the drain pad.

48. The method of claim 44, wherein the substrate contact comprises an ohmic contact, the method further comprising:

forming a non-ohmic backside substrate contact on a second surface of the substrate, opposite the first surface of the substrate;

forming a drain pad electrically coupled to the drain region; and

forming a wire electrically coupling the drain pad to the backside substrate contact.

49. The method of claim 40, wherein the substrate comprises a semi-insulating substrate or an n-type substrate and wherein the contact via hole extends through a first surface of the substrate to a second surface of the substrate, opposite the first surface of the substrate.

50. The method of claim 49, wherein the substrate comprises an n-type silicon carbide (SiC) substrate or a semi-insulating SiC substrate.

51. The method of claim 49, further comprising:

forming first and second ohmic contacts on the source region and the drain region, respectively, that respectively define a source contact and a drain contact;

forming a backside substrate contact on the second surface of the substrate, wherein the contact via hole exposes a portion of the backside substrate contact.

52. The method of claim 51, further comprising:

a first overlayer in the contact via hole and extending to the drain contact and the backside substrate contact, the first overlayer electrically coupling the drain contact to the backside substrate contact to electrically couple the drain region to the substrate.

53. The method of claim 51, wherein the drain region is electrically coupled to a drain pad and wherein the contact via hole is at least partially disposed in the drain pad.

54. The method of claim 40, further comprising forming an n-type conductivity channel layer on the substrate, the gate contact being disposed on the n-type conductivity layer.

55. The method of claim 54, wherein forming the n-type conductivity channel layer comprises forming an n-type conductivity silicon carbide (SiC) channel layer, wherein the gate extends into the n-type conductivity SiC channel layer.

56. The method of claim 55, wherein the gate contact is disposed in a single recess.

57. The method of claim 55, wherein the gate contact is disposed in a double recess.

58. The method of claim 54, wherein the contact via hole comprises a first contact via hole, the method further comprising:

forming a p-type conductivity region beneath the source region and having an end that extends towards the drain region, the p-type conductivity region being spaced apart from the n-type conductivity channel layer and being electrically coupled to the source region; and

forming a second contact via hole adjacent the source region that exposes the p-type conductivity region; and

forming an ohmic contact on the exposed portion of the p-type conductivity region.

59. The method of claim 54, further comprising:

implanting n-type dopants in the source region and the drain region so as to provide highly doped regions having higher carrier concentrations than the n-type conductivity channel layer, wherein first and second ohmic contacts that respectively define a source contact and a drain contact are disposed on the source region and the drain region, respectively.

60. The method of claim 59, wherein implanting n-type dopants further comprises annealing the n-type dopants to activate the n-type dopants.

61. The method of claim 54, further comprising:

forming a first buffer layer on the substrate; and

forming a second buffer layer on the first buffer layer, wherein the n-type conductivity channel layer is on the second buffer layer and wherein the contact via hole extends through the drain region, the n-type channel region and the first and second buffer layers to a first surface of the substrate.

62. The method of claim 61, wherein the contact via hole further extends through the first surface of the substrate to a second surface of the substrate, opposite the first surface of the substrate.

63. The method of claim 54, wherein forming the n-type conductivity channel layer comprises:

forming a first n-type conductivity channel layer on the substrate; and

forming a second n-type conductivity channel layer on the first n-type conductivity channel layer.

64. The method of claim 54, wherein forming the n-type conductivity channel layer comprises:

forming first, second and third n-type conductivity SiC channel layers and wherein the first, second and third n-type conductivity channel layers have respective first, second and third carrier concentrations.

65. The method of claim 40, wherein the substrate comprises n-type conductivity or semi-insulating gallium arsenide (GaAs) and n-type conductivity or semi-insulating gallium Nitride (GaN).

66. The method of claim 40, wherein forming the contact via hole comprises:

etching a contact window for the contact via hole in an oxide layer on the drain region; and

etching the n-type conductivity channel layer, and first and second buffer layers through the contact window to expose the substrate.