Trench MIS device and method for manufacturing trench MIS device

• US 20060091453A1
• Filed: 08/23/2005
• Published: 05/04/2006
• Est. Priority Date: 08/26/2004
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsuda, Noboru, Tsuchitani, Masanobu, Takahashi, Koichi, Kawamura, Keiko
• Application Number:
  US11/208,619
• Publication Number:
  US 20060091453A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/515 with cavities, e.g. containing a gas
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MIS device includes a drain region, a base region disposed on the drain region, the base region having a channel face, a source region disposed on the base region, the source region having a source end face, the source end face being continuous with the channel face, a gate insulator disposed along the channel face and the source end face, a gate electrode disposed opposite to the channel face through the gate insulator, and a cavity portion provided in the drain region, the cavity portion being opposite to the gate electrode.

Claims

1. A trench MIS device comprising:

a drain region;

a base region disposed on the drain region, the base region having a channel face;

a source region disposed on the base region, the source region having a source end face, the source end face being continuous with the channel face;

a gate insulator disposed continuously along the channel face and the source end face;

a gate electrode disposed opposite to the channel face through the gate insulator; and

a cavity portion provided in the drain region below the gate electrode, the cavity portion being opposite to the gate electrode.

2. The device of claim 1, wherein the gate insulator extends to a cavity bottom of the cavity portion from the channel face and the source end face via a cavity sidewall of the cavity portion.

3. The device of claim 2, wherein the channel face, the source end face, and the cavity sidewall of the cavity portion define a trench sidewall, the cavity bottom of the cavity portion defines a trench bottom, and a trench having the trench sidewall and the trench bottom establishes a constricted shape in a middle portion.

4. The device of claim 1, wherein the gate insulator extends to a portion between the cavity portion and the gate electrode.

5. The device of claim 4, wherein the gate insulator extends to an inner wall of the cavity portion.

6. The device of claim 1, wherein a sectional contour of the cavity portion is defined by a curved line.

7. The device of claim 1, the cavity portion has an inversely tapered shape, the inversely tapered shape broadening at a cavity bottom of the cavity portion.

8. A method for manufacturing a trench MIS device including:

preparing a semiconductor substrate on which a drain region, a base region, and a source region are formed in order;

forming a trench extending from the source region to the drain region via the base region, the trench having a trench sidewall and a trench bottom;

forming a gate insulator on the trench sidewall and the trench bottom;

forming a polycrystalline silicon film on the gate insulator, the polycrystalline silicon film being doped with a plurality of dapants; and

forming a cavity portion in a lower portion of the trench and a gate electrode derived from the polycrystalline silicon film in an upper portion of the trench by a diffusion of a plurality of silicon atoms in the polycrystalline silicon film, the diffusion being caused by a hydrogen annealing of the polycrystalline silicon film.

9. The method of claim 8, further including removing a portion of the polycrystalline silicon film formed on the gate insulator disposed on the trench bottom of the trench before the hydrogen annealing of the polycrystalline silicon film.

10. The method of claim 9, wherein an anisotropic etching is employed to remove the portion of the polycrystalline silicon film.

11. The method of claim 9, wherein the hydrogen annealing of the polycrystalline silicon film is performed in a reduced pressure.

12. The method of claim 9, wherein the hydrogen annealing of the polycrystalline silicon film is performed at 1100 to 1200 degree C. for 10 to 30 minutes.

13. The method of claim 8, further including changing a shape of the trench by a diffusion of a plurality of silicon atoms inside the trench sidewall by a hydrogen annealing of the trench before the gate insulator is formed.

14. The method of claim 13, wherein the trench is filled with the polycrystalline silicon film via the gate insulator after the hydrogen annealing of the trench and a plurality of voids in the polycrystalline silicon film is segregated to form the cavity portion by the hydrogen annealing of the polycrystalline silicon film.

15. The method of claim 13, wherein a sectional contour of the trench defined by the trench sidewall has a constricted shape after the hydrogen annealing of the trench.

16. The method of claim 15, wherein the hydrogen annealing of the trench is performed at 900 to 1000 degree C. for one to five minutes.

17. A method for manufacturing a trench MIS device including:

forming a drain region on a semiconductor substrate;

forming a cave in the drain region;

diffusing a plurality of silicon atoms inside a cave sidewall of the cave by a hydrogen annealing of the cave so as to fill an upper portion of the cave with the silicon atoms to form a cavity portion in the drain region;

forming a trench above the cavity portion in the drain region, the trench being not penetrating to the cavity portion;

forming a gate insulator on a trench sidewall of the trench; and

forming a gate electrode on the gate insulator by filling the trench with an electrically conductive material.

18. The method of claim 17, further including doping a plurality of dopants into the drain region to provide a base region and a source region on the drain region after the cavity portion is formed.

19. The method of claim 17, wherein the hydrogen annealing of the cave is performed in a reduced pressure.

20. The method of claim 17, wherein the hydrogen annealing of the cave is performed at 1100 to 1200 degree C. for 10 to 30 minutes.