Trench MOSFET and method of manufacturing same

• US 20060091455A1
• Filed: 10/28/2005
• Published: 05/04/2006
• Est. Priority Date: 10/29/2004
• Status: Abandoned Application

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Adan, Alberto O.
• Application Number:
  US11/260,236
• Publication Number:
  US 20060091455A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET of the present invention has a trench region on a semiconductor substrate. The semiconductor substrate contains: a substrate which is a p-type heavily doped drain region; an epitaxial layer which is a p-type lightly doped drain region; a n-type body region; and a p-type source diffusion region, the regions being formed in this order. Further, a source diffusion region which is insulated from the trench region is provided to cover the trench region. The trench MOSFET has a reduced ON resistance.

Claims

1. A trench MOSFET, comprising a trench region on a semiconductor substrate,

the substrate containing:

a heavily doped drain region of a first conduction type;

a lightly doped drain region of the first conduction type;

a channel body region of a second conduction type; and

a source region of the first conduction type, the regions being formed in this order and adjacent to each other,

the trench region being covered with, and insulated from, the source region.

2. The trench MOSFET of claim 1, wherein:

the trench region extends through the channel body region and the lightly doped drain region to the heavily doped drain region;

there is provided a gate electrode for controlling channel conduction in a part surrounded by the channel body region; and

there is provided an insulator region in a part surrounded by the lightly doped drain region.

3. The trench MOSFET of claim 2, wherein a top of the semiconductor substrate is separated by substantially equal distances from a bottom of the gate electrode and from an interface between the heavily doped drain region and the lightly doped drain region.

4. The trench MOSFET of claim 1, wherein:

the trench region extends through the heavily doped drain region and the lightly doped drain region to the channel body region;

there is provided an upper gate electrode for controlling channel conduction in a part surrounded by the heavily doped drain region; and

there is provided a lower electrode electrically separated from the upper gate electrode in a part surrounded by the lightly doped drain region.

5. The trench MOSFET of claim 4, wherein an output of an amplifier electrically driving the lower electrode is associated with a voltage applied to the upper gate electrode.

6. The trench MOSFET of claim 1, wherein the trench region has a vertical wall on which a gate inducing channel is formed.

7. The trench MOSFET of claim 1, having a channel length defined by a difference between a depth of the channel body region and a junction depth of the source region.

8. The trench MOSFET of claim 1, wherein the semiconductor substrate is made of silicon.

9. The trench. MOSFET of claim 1, wherein the lightly doped drain region is made of epitaxial SiGe.

10. The trench MOSFET of claim 1, wherein

3×

10¹¹ (atoms/cm²)≦

Ts×

Ndrift≦

3×

10¹² (atoms/cm²)

where Ndrift is an impurity doping level in the lightly doped drain region, and Ts is an interval between trench regions.

11. A method of manufacturing a trench MOSFET including a trench region on a semiconductor substrate,

the substrate containing:

a heavily doped drain region of a first conduction type;

a lightly doped drain region of the first conduction type;

a channel body region of a second conduction type; and

a source region of the first conduction type, the regions being formed in this order and so that adjacent regions are in contact with each other,

the method comprising the sequential steps of;

forming an insulating film on the trench region;

providing an amorphous silicon layer on the trench region on which the insulating film is formed and on the channel region; and

crystallizing the amorphous silicon layer, to form the source region.

12. The method of claim 11, wherein the amorphous silicon is crystallized by thermal processing in an atmosphere of an inactive gas.

13. The method of claim 12, wherein:

the inactive gas is nitrogen gas; and

the thermal processing is carried out at an ambient temperature of 550°

C. to 600°

C., inclusive.

14. A method of manufacturing a trench MOSFET including a trench region on a semiconductor substrate,

the substrate containing:

a heavily doped drain region of a first conduction type;

a lightly doped drain region of the first conduction type;

a channel body region of a second conduction type; and

a source region of the first conduction type, the regions being formed in this order and so that adjacent regions are in contact with each other,

the method comprising the sequential steps of;

forming an insulating film on the trench region; and

providing a polysilicon layer on the trench region on which the insulating film is formed and on the channel region, to form the source region.