Chip-on-board package having flip chip assembly structure and manufacturing method thereof

• US 20060091511A1
• Filed: 07/13/2005
• Published: 05/04/2006
• Est. Priority Date: 11/03/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Sa-Yoon, Kim, Dong-Han, Lee, Seok-Won
• Granted Patent: US 7,315,086 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/81201 Compression bonding
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/90 Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/90 Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 1/112 : directly combined with via connections
• CPC Class Codes: H05K 1/189 : characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 2201/0394 : Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

A chip-on-board (COB) package has a flip chip assembly structure and is used for an integrated circuit (IC) card. The COB package has conductive patterns as contact terminals on an outer surface of a non-conductive film, and an IC chip on an inner surface of the film. The film has a number of holes through which the conductive patterns are partly exposed. A number of conductive bumps on an active surface of the IC chip face the inner surface of the film and enter corresponding holes in the non-conductive film to mechanically join and electrically couple to the conductive patterns. The disclosed COB package and a related manufacturing method allow a reduction in production cost, simplified process, better electrical connections, and improved reliability.

Claims

1. A chip-on-board package comprising:

a non-conductive film having a first surface, a second surface opposite the first surface, and a plurality of holes;

conductive patterns formed on the first surface of the non-conductive film with a portion of the conductive patterns exposable through at least one of the holes of the non-conductive film; and

an integrated circuit chip having an active surface facing the second surface of the non-conductive film and having a plurality of conductive bumps on the active surface, at least one of the plurality of conductive bumps being insertable into the at least one of the holes of the non-conductive film to mechanically join and electrically couple therethrough.

2. The package of claim 1, wherein a height of the at least one of the conductive bumps exceeds a thickness of the non-conductive film.

3. The package of claim 2, wherein the height of the at least one of the conductive bumps is between about 30 μ

m and about 50 μ

m and wherein the thickness of the non-conductive film is between about 10 μ

m and about 20 μ

m.

4. The package of claim 1, wherein the at least one of the conductive bumps comprise gold.

5. The package of claim 1, wherein the non-conductive film comprises at least one of epoxy and polyimide.

6. The package of claim 1, wherein a width of the at least one of the conductive bumps is about 20 μ

m.

7. The package of claim 1, wherein a diameter of the at least one of the holes is about 1 mm.

8. The package of claim 1, wherein the at least one of the plurality of conductive bumps mechanically joins and electrically couples to the portion of the conductive patterns exposed through the at least one hole of the plurality of holes.

9. The package of claim 8, wherein a height of the at least one of the conductive bumps exceeds a thickness of the non-conductive film.

10. The package of claim 9, wherein the height of the at least one of the conductive bumps is between about 30 μ

m and about 50 μ

m and wherein the thickness of the non-conductive film is between about 10 μ

m and about 20 μ

m.

11. The package of claim 9, wherein a ratio of the thickness of the non-conductive film to the height of the at least one of the conductive bumps is between about 0.33 and about 0.40.

12. The package of claim 8, wherein the at least one of the conductive bumps comprise gold and wherein the non-conductive film comprises at least one of epoxy and polyimide.

13. The package of claim 8, wherein a width of the at least one of the conductive bumps is about 20 μ

m.

14. The package of claim 8, wherein a diameter of the at least one of the holes is about 1 mm.

15. A method of manufacturing a chip-on-board package, the method comprising:

forming a plurality of holes through a non-conductive film having a first surface and a second surface opposite the first surface;

forming conductive patterns on the first surface of the non-conductive film and exposed through the holes;

forming conductive bumps on an active surface of an integrated circuit chip; and

disposing the integrated circuit chip relative to the second surface of the non-conductive film to make insertable the conductive bumps into the holes of the non-conductive film.

16. A method of claim 15, further comprising mechanically joining and electrically coupling the conductive bumps and the conductive patterns by way of the holes.

17. The method of claim 16, wherein the forming of the holes is carried out using a punch.

18. The method of claim 16, wherein the forming of the conductive patterns includes bonding a metal plate to the first surface of the non-conductive film and photo-etching the metal plate.

19. The method of claim 16, wherein the forming of the conductive bumps is carried out using at least one of electroplating and stud bumping.

20. The method of claim 16, further comprising:

interposing a non-conductive adhesive between the active surface of the integrated circuit chip and the second surface of the non-conductive film.

21. An integrated circuit card comprising:

a flexible card body; and

a chip-on-board package mounted in the card body through one surface of the card body, the chip-on-board package including;

a non-conductive film having a first surface, a second surface opposite to the first surface, and a plurality of holes therethrough;

a plurality of metal elements corresponding to the plurality of holes, each metal element being disposed on the first surface of the non-conductive film and exposed through a corresponding one of the plurality of holes;

an integrated circuit chip having an active surface facing the second surface of the non-conductive film; and

a plurality of conductive bumps corresponding to the plurality of holes, formed on the active surface of the integrated circuit chip, and insertable into a corresponding one of the plurality of holes to mechanically join and electrically couple therethrough with a corresponding one of the plurality of metal elements thereby made available as an exposed contact terminal of the integrated circuit card.

22. The integrated circuit card of claim 21, wherein a height of the at least one of the plurality of conductive bumps exceeds a thickness of the non-conductive film.

23. The integrated circuit card of claim 22, wherein the height of the at least one of the conductive bumps is between about 30 cm and about 50 cm and wherein the thickness of the non-conductive film is between about 10 μ

m and about 20 μ

m.

24. The integrated circuit card of claim 22, wherein a ratio of the thickness of the non-conductive film to the height of at least one of the conductive bumps is between about 0.33 and about 0.40.

25. The integrated circuit card of claim 21, further comprising a non-conductive adhesive interposed between the active surface of the integrated circuit chip and the second surface of the non-conductive film.

26. A chip-on-board package comprising:

a non-conductive film having plurality of holes coupling a first surface and a second surface thereof;

a plurality of metal elements formed on the first surface of the non-conductive film, at least one of the plurality of metal elements being exposed through a corresponding at least one of the plurality of holes; and

an integrated circuit chip having an active surface facing the second surface of the non-conductive film and presenting thereon a plurality of conductive bumps corresponding to the plurality of holes, at least one of the plurality of conductive bumps being insertable into a corresponding one of the plurality of holes.

27. A chip-on-board package according to claim 26, wherein the at least one of the plurality of conductive bumps mechanically contacts and electrically couples to the corresponding at least one of the plurality of metal elements.

28. A chip-on-board package according to claim 26, wherein a height of the at least one of the conductive bumps exceeds a thickness of the non-conductive film.

29. A chip-on-board package according to claim 28, wherein a ratio of the thickness of the non-conductive film to the height of the at least one of the conductive bumps is between about 0.20 and about 0.66.

30. A chip-on-board package according to claim 28, wherein the height of the at least one of the conductive bumps is between about 30 μ

m and about 50 μ

m and wherein the thickness of the non-conductive film is between about 10 μ

m and about 20 μ

m.

31. A chip-on-board package according to claim 26, wherein the at least one of the conductive bumps comprise gold.

32. A chip-on-board package according to claim 26, wherein the non-conductive film comprises at least one of epoxy and polyimide.

33. A chip-on-board package according to claim 26, wherein a width of the at least one of the conductive bumps is about 20 μ

m.

34. A chip-on-board package according to claim 26, wherein a diameter of the at least one of the holes is about 1 mm.

35. A chip-on-board package according to claim 26, wherein each of the plurality of conductive bumps is disposed within the corresponding one of the plurality of holes and each mechanically contacts and electrically couples to the corresponding one of the metal elements.