Plastic package and semiconductor component comprising such a plastic package, and method for its production

• US 20060091522A1
• Filed: 10/11/2005
• Published: 05/04/2006
• Est. Priority Date: 10/11/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Bauer, Michael, Bachmaier, Ulrich, Hagen, Robert-Christian
• Granted Patent: US 7,554,196 B2
• Time in Patent Office: Days
• US Class Current: 257/693
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/82103 using laser direct writing
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/295 containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A plastic package and to a semiconductor component including such a plastic package, as well as to a method for its production is disclosed. In one embodiment, the plastic package includes plastic outer faces, which include lower outer contact faces on a lower side of the plastic package and upper outer contact faces on an upper side, which are connected together via outer conductor tracks. The conductor tracks include conduction paths which are formed on exposed conducting deposits in the plastic package.

Claims

1. A plastic package comprising:

a semiconductor component with plastic outer faces, which comprises;

a lower side having lower outer contact faces; and

an upper side having upper outer contact faces, wherein the lower and upper outer contact faces are electrically connected together via conductor tracks, and wherein the conductor tracks comprise a metal layer which is arranged on conduction paths, the conduction paths comprising exposed conducting deposits in the plastic of the package.

2. The plastic package according to claim 1, wherein the conductor tracks are arranged on the plastic outer faces.

3. The plastic package according to claim 1, wherein the conductor tracks are arranged in access openings through the plastic package.

4. The plastic package according to claim 1, wherein the exposed conducting deposits on the conduction paths are covered with a lower metal layer a few nanometers thick.

5. The plastic package according to claim 1, wherein the exposed conducting deposits on the conduction paths are covered with an upper metal layer a few micrometers thick.

6. The plastic package according to claim 1, wherein the exposed conducting deposits in the plastic comprise metal complexes.

7. The plastic package according to claim 1, wherein the exposed conducting deposits in the plastic comprise conducting nanoparticles.

8. The plastic package according to claim 1, wherein the nanoparticles are fullerenes.

9. The plastic package according to claim 1, wherein the exposed conducting deposits in the plastic comprise metalorganic compounds.

10. A semiconductor component comprising:

a plastic package having a semiconductor component with plastic outer faces, which comprises;

a lower side having lower outer contact faces; and

an upper side having upper outer contact faces, wherein the lower and upper outer contact faces are electrically connected together via conductor tracks, and wherein the conductor tracks comprise a metal layer which is arranged on conduction paths, the conduction paths comprising exposed conducting deposits in the plastic of the package.

11. The semiconductor component according to claim 10, wherein the plastic package comprises on its lower side a wiring substrate which, in its edge region, comprises through-contacts which are electrically connected to the outer conductor tracks on the upper side of the wiring substrate and are in electrical connection with a wiring structure on the lower side of the wiring substrate, the wiring structure connecting the through-contacts to the lower outer contact faces.

12. The semiconductor component according to claim 10, wherein the plastic of the plastic package comprises deposits of a metalorganic compound, whose metallic constituents are exposed in the conduction paths and covered by a metal layer.

13. The semiconductor component according to claim 10, wherein the plastic of the package comprises deposits of electrically conducting nanoparticles, which are partially exposed in the conduction paths and covered by a metal layer.

14. The semiconductor component according to claim 10, wherein the size and arrangement of the upper outer contact faces on the upper side of the semiconductor component corresponds to the size and arrangement of surface-mountable outer contacts of a semiconductor component to be stacked.

19. The semiconductor module according to claim 11, wherein the semiconductor module comprises at least one logic component, including a microprocessor chip package and a memory component.

15. A semiconductor module comprising:

a semiconductor base component; and

at least one semiconductor component stacked thereon, the semiconductor base component of the semiconductor component stack comprising a semiconductor component a plastic package having a semiconductor component with plastic outer faces, which comprises a lower side having lower outer contact faces, and an upper side having upper outer contact faces, wherein the lower and upper outer contact faces are electrically connected together via conductor tracks, and wherein the conductor tracks comprise a metal layer which is arranged on conduction paths, the conduction paths comprising exposed conducting deposits in the plastic of the package.

16. The semiconductor module according to claim 15, wherein the stacked semiconductor component comprises surface-mountable outer contacts.

17. The semiconductor module according to claim 15, wherein the semiconductor module comprises memory components.

18. The semiconductor module according to claim 17, wherein the memory component is a DRAM.

20. A method for producing a plastic package with plastic outer faces, which comprises lower outer contact faces arranged on a lower side and upper outer contact faces arranged on an upper side, wherein the lower and upper outer contact faces are electrically connected together via conductor tracks, and wherein the method comprises:

mixing a polymer of a plastic package compound with a deposit material, which releases electrically conducting material when irradiated;

forming a plastic package with the plastic package compound;

selectively exposing electrically conducting material to form conduction paths comprising isolatedly arranged conductive positions between outer contact-face regions on the upper side of the plastic package and contact terminal faces on a wiring substrate;

amplifying the electrically conducting material to form a lower metal layer; and

electrolytically depositing an upper metal layer a few micrometers thick on the lower metal layer to form a wiring structure between lower and upper outer contact faces.

21. The method according to claim 20, wherein a metalorganic compound is added to the plastic as deposits.

22. The method according to claim 20, wherein electrically conducting nanoparticles are added to the plastic as deposits.

23. The method according to claim 20, wherein the plastic outer faces of the plastic package are irradiated with photons, ions and/or electrons in order to selectively expose electrically conducting material in regions of the conduction paths.

24. The method according to claim 20, wherein in order to selectively expose electrically conducting material to form conduction paths through the plastic package, laser ablation is carried out through the plastic of the package at positions intended for through-contacts and the access opening is then electrolytically filled with the electrically conducting material of the upper metal layer.

25. The plastic package according to claim 20, wherein the amplification of the electrically conducting material to form a lower metal layer is carried out by currentless deposition of a lower structured metal layer a few nanometers thick on the electrically conducting material, the structuring being dictated by selective exposure of electrically conducting material in isolatedly arranged conductive positions.

26. The plastic package according to claim 20, wherein the amplification of the electrically conducting material to form a lower metal layer is carried out by means of sputtering technology, vapor deposition technology and/or plasma deposition on the plastic outer faces of the package or on the walls of access openings through the plastic package, and then the lower metal layer is structured to form conduction paths by means of photolithographic technology.

27. A plastic package having a semiconductor component, comprising:

means for providing plastic outer faces, which comprises a lower side having lower outer contact faces, and an upper side having upper outer contact faces, wherein the lower and upper outer contact faces are electrically connected together via conductor tracks, and wherein the conductor tracks comprise a metal layer which is arranged on conduction paths, the conduction paths comprising exposed conducting deposits in the plastic of the package.