Secure OTP using external memory
First Claim
1. A semiconductor integrated circuit for restricting data access to and from an external memory that includes one or more regions and stores data in an encrypted form, the circuit comprising:
- a first cryptographic circuit for encrypting data transmitted from the circuit to the external memory and for decrypting data transmitted from the external memory to the circuit, the encrypting and decrypting being performed using a secret encryption or decryption key; and
one or more fuses, each fuse corresponding to one of the regions of the external memory, and which are initially in a first state and which may be irreversibly changed to a second state;
in which the circuit is arranged to cause a change in state of a selected fuse from the first state to the second state, the selected fuse corresponding to a region of the external memory to which data has been written-, and in which the circuit is further arranged to block data writes to the external memory if data is being written to a region for which the corresponding fuse is in the second state.
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Accused Products
Abstract
A set-top-box has on-chip OTP memory emulated using an external flash memory and a series of on-chip fuses. The external memory is comprised of one or more regions, each having its own unique region identification. Each on-chip fuse corresponds to one of the memory regions and comprises a component which can be caused to change to a particular (blown) state irreversibly. When data first needs to be written to a region of the external memory, the identification of that region is appended to the data itself together with a parity field and a validity field. The resultant data packet is then encrypted by a cryptographic circuit using a secret key unique to the set-top-box and the encrypted data packet is written to the specified region of the external memory. Then, the on-chip fuse corresponding to the region that has been written to is irreversibly blown, effectively locking that region.
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Citations
45 Claims
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1. A semiconductor integrated circuit for restricting data access to and from an external memory that includes one or more regions and stores data in an encrypted form, the circuit comprising:
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a first cryptographic circuit for encrypting data transmitted from the circuit to the external memory and for decrypting data transmitted from the external memory to the circuit, the encrypting and decrypting being performed using a secret encryption or decryption key; and
one or more fuses, each fuse corresponding to one of the regions of the external memory, and which are initially in a first state and which may be irreversibly changed to a second state;
in which the circuit is arranged to cause a change in state of a selected fuse from the first state to the second state, the selected fuse corresponding to a region of the external memory to which data has been written-, and in which the circuit is further arranged to block data writes to the external memory if data is being written to a region for which the corresponding fuse is in the second state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A set-top-box, comprising:
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an external memory that includes one or more regions and stores data in an encrypted form; and
a semiconductor integrated circuit for restricting data access to and from the external memory, the circuit including;
a first cryptographic circuit for encrypting data transmitted from the circuit to the external memory and for decrypting data transmitted from the external memory to the circuit, the encrypting and decrypting being performed using a secret encryption or decryption key; and
one or more fuses, each fuse corresponding to one of the regions of the external memory, and which are initially in a first state and which may be irreversibly changed to a second state;
in which the circuit is arranged to cause a change in state of a selected fuse from the first state to the second state, the selected fuse corresponding to a region of the external memory to which data has been written and in which the circuit is further arranged to block data writes to the external memory if data is being written to a region for which the corresponding fuse is in the second state. - View Dependent Claims (27, 28, 29, 41)
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30. A method for restricting data access to and from an external memory which comprise one or more regions and which stores data in an encrypted form, the method comprising the steps of:
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encrypting a data packet using a unique key;
selecting a first region of the external memory to which the encrypted data packet is to be written;
determining whether the selected first region has already been written to by determining a state of a fuse corresponding to the selected first region;
writing the encrypted data packet to the selected first region if the fuse corresponding to the selected region is in a first state indicating that the selected first region has not already been written to;
irreversibly changing the state of the fuse corresponding to the selected first region from the first state to a second state when the encrypted data packet has been written to the selected first region; and
blocking the writing of the encrypted data packet if the fuse corresponding to the selected first region is in the second state indicating that the selected first region has already been written to. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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42. A semiconductor integrated circuit for restricting data access to and from an external memory that includes one or more regions, the circuit comprising:
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one or more fuses, each fuse corresponding to a respective one of the regions of the external memory, and which are initially in a first state and which may be irreversibly changed to a second state; and
means for blocking writing to the one of the one or more regions in response to determining that the fuse corresponding to the one of the one or more regions is in the second state. - View Dependent Claims (43, 44, 45)
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Specification