Multiport semiconductor memory device

• US 20060092740A1
• Filed: 10/17/2005
• Published: 05/04/2006
• Est. Priority Date: 10/29/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nii, Koji
• Granted Patent: US 7,260,018 B2
• Time in Patent Office: Days
• US Class Current: 365/221
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD−Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports PA and PB simultaneously access the same row, the voltage level of word lines WLA, WLB is set to power supply voltage VDD−Vtp. Thus, a driving current amount of a memory cell is reduced, thereby preventing a reduction in a current ratio of a transistor. As a result, deterioration of SNM can be prevented.

Claims

1. A semiconductor memory device comprising:

a memory array having a plurality of memory cells arranged in rows and columns;

first and second ports receiving and transmitting input/output signals independent of each other; and

a selection circuit capable of simultaneously accessing said memory array according to addresses respectively input to said first and second ports,

said memory array including

a plurality of first and second word lines provided respectively corresponding to memory cell rows, and

a plurality of first and second bit lines provided respectively corresponding to memory cell columns,

each of said memory cells including

a flip-flop circuit for setting first and second storage nodes to one and the other of first and second potential levels, respectively, according to data to be stored,

a first gate transistor having its gate electrically coupled to a corresponding first word line for electrically coupling a corresponding first bit line to said flip-flop circuit, and

a second gate transistor having its gate electrically coupled to a corresponding second word line for electrically coupling a corresponding second bit line to said flip-flop circuit,

said selection circuit including

first and second row decoders provided respectively corresponding to said first and second ports for outputting respective row selection instructions according to input addresses, and

a plurality of word drivers provided respectively corresponding to memory cell rows, each for driving corresponding first and second word lines according to row selection results from said first and second row decoders, wherein

when receiving an input of a row selection instruction from one of said first and second row decoders, each of said word drivers sets a voltage level of a word line corresponding to the one to a first voltage level, and when receiving inputs of row selection instructions from both of said first and second row decoders, each of said word drivers sets respective voltage levels of first and second word lines to a second voltage level lower than said first voltage level.

2. The semiconductor memory device according to claim 1, wherein each of said word drivers includes

first and second word driver units provided respectively corresponding to corresponding first and second word lines for setting a voltage level of said corresponding first and second word lines to either one of first and second voltage levels in response to row selection instructions respectively input from said first and second row decoders, and

a detection circuit detecting inputs of row selection instructions from both of said first and second row decoders to instruct said first and second word driver units to set a voltage level of said corresponding first and second word lines to the second voltage level.

3. A semiconductor memory device comprising:

a memory array having a plurality of memory cells arranged in rows and columns;

first and second ports receiving and transmitting input/output signals independent of each other; and

a selection circuit capable of simultaneously accessing said memory array according to addresses respectively input to said first and second ports,

said memory array including

a plurality of first and second word lines provided respectively corresponding to memory cell rows, and

a plurality of first and second bit lines provided respectively corresponding to memory cell columns,

each of said memory cells including

a flip-flop circuit for setting first and second storage nodes to one and the other of first and second potential levels, respectively, according to data to be stored,

a first gate transistor having its gate electrically coupled to a corresponding first word line for electrically coupling a corresponding first bit line to said flip-flop circuit, and

a second gate transistor having its gate electrically coupled to a corresponding second word line for electrically coupling a corresponding second bit line to said flip-flop circuit,

said semiconductor memory device further comprising power supply lines provided respectively corresponding to memory cell rows, each supplying an operating voltage to said flip-flop circuit of each memory cell included in a corresponding memory cell row,

said selection circuit including

first and second row decoders provided respectively corresponding to said first and second ports for outputting respective row selection instructions according to input addresses, and

a plurality of word drivers provided respectively corresponding to memory cell rows, each driving corresponding first and second word lines according to row selection results from said first and second row decoders and also driving a corresponding power supply line, wherein

each of said word drivers sets a voltage level of a corresponding power supply line to a first voltage level when receiving an input of a row selection instruction from one of said first and second row decoders, and sets a voltage level of said corresponding power supply line to a second voltage level higher than said first voltage level when receiving inputs of row selection instructions from both of said first and second row decoders.

4. The semiconductor memory device according to claim 3, wherein

each of said word drivers includes

first and second word driver units provided respectively corresponding to corresponding first and second word lines for setting a voltage level of said corresponding first and second word lines to said first voltage level in response to row selection instructions respectively input from said first and second row decoders, and

a voltage switching circuit provided corresponding to a corresponding power supply line for detecting inputs of row selection instructions from both of said first and second row decoders to switch a voltage level of said corresponding power supply line from said first voltage level to said second voltage level.

5. A semiconductor memory device comprising:

a memory array having a plurality of memory cells arranged in rows and columns;

first and second ports receiving and transmitting input/output signals independent of each other; and

a selection circuit capable of simultaneously accessing said memory array according to addresses respectively input to said first and second ports,

said memory array including

a plurality of first and second word lines provided respectively corresponding to memory cell rows, and

a plurality of first and second bit lines provided respectively corresponding to memory cell columns,

each of said memory cells including

a flip-flop circuit for setting first and second storage nodes to one and the other of first and second potential levels, respectively, according to data to be stored,

a first gate transistor having its gate electrically coupled to a corresponding first word line for electrically coupling a corresponding first bit line to said flip-flop circuit, and

a second gate transistor having its gate electrically coupled to a corresponding second word line for electrically coupling a corresponding second bit line to said flip-flop circuit,

said selection circuit including

first and second row decoders provided respectively corresponding to said first and second ports for outputting respective row selection instructions according to input addresses, and

a plurality of word drivers provided respectively corresponding to memory cell rows, each for driving corresponding first and second word lines according to row selection results from said first and second row decoders, wherein

when receiving an input of a row selection instruction from one of said first and second row decoders, each of said word drivers drives a word line corresponding to the one, and when receiving inputs of row selection instructions from both of said first and second row decoders, each of said word drivers drives either one of the word lines.

6. The semiconductor memory device according to claim 5, wherein

each of said word driver includes first and second word driver units provided respectively corresponding to corresponding first and second word lines for driving said corresponding first and second word lines to a prescribed voltage level in response to row selection instructions respectively input from said first and second row decoders, and

one of said first and second word driver units includes stop means for detecting inputs of row selection instructions from both of said first and second row decoders to stop driving of a corresponding one of the word lines.

7. The semiconductor memory device according to claim 5, further comprising:

an address comparison circuit determining whether addresses respectively input to said first and second ports are addresses corresponding to a same memory cell row; and

short-circuiting circuits provided respectively corresponding to memory cell columns, each short-circuiting corresponding first and second bit lines according to a determination result of said address comparison circuit.

8. The semiconductor memory device according to claim 5, further comprising:

first and second reading/writing circuits provided respectively corresponding to said first and second ports and electrically coupled to said plurality of first and second bit lines, respectively, for executing data reading and data writing;

an address comparison circuit determining whether addresses respectively input to said first and second ports are addresses corresponding to a same memory cell row; and

a switching circuit provided corresponding to either one of said first and second reading/writing circuits for switching an electrical connection with a corresponding one bit line to an electrical connection with the other bit line according to a determination result of said address comparison circuit.