Method and system for processing wireless digital multimedia

• US 20060092893A1
• Filed: 08/30/2005
• Published: 05/04/2006
• Est. Priority Date: 11/03/2004
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Hardacker, Robert, Unger, Robert Allan, Champion, Mark
• Granted Patent: US 7,228,154 B2
• Time in Patent Office: Days
• US Class Current: 370/338
• CPC Class Codes: G09G 2370/045 using multiple communication channels, e.g. parallel and serial
• CPC Class Codes: G09G 2370/047 using display data channel standard [DDC] communication
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 2370/12 Use of DVI or HDMI protocol in interfaces along the display data pipeline
• CPC Class Codes: G09G 2370/16 Use of wireless transmission of display information
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H04L 12/2805 Home Audio Video Interoperability [HAVI] networks
• CPC Class Codes: H04L 65/1101 Session protocols
• CPC Class Codes: H04L 67/12 specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
• CPC Class Codes: H04N 21/43635 HDMI
• CPC Class Codes: H04N 21/43637 involving a wireless protocol, e.g. Bluetooth, RF or wireless LAN [IEEE 802.11] arrangements for wireless networking or broadcasting of information in indoor or near-field type systems H04B10/114

Abstract

A transmit digital processing system for wireless transmission of HDMI and/or DVI data using an FPGA. The FPGA converts the data into two data streams and includes a front end component multiplexing video data with control data. A complementary receive FPGA is also disclosed.

Claims

1. A system for wirelessly transmitting HDMI data from a source to a display, comprising:

a DVI receiver receiving HDMI data;

a transmit digital processing system receiving an output of the DVI receiver;

a wireless transmitter receiving an output of the transmit digital processing system and wirelessly sending it to a receiver;

a receive digital processing system receiving an output of the receiver;

a DVI transmitter receiving an output of the receive digital processing system; and

a display receiving an output of the DVI transmitter and displaying, in response, the HDMI data, including audibly displaying audio data present in the HDMI data.

2. A transmit digital processing system for wireless transmission of HDMI and/or DVI data, the system converting the data into two data streams, wherein the system includes a front end component multiplexing video data with control data.

3. The system of claim 2, comprising a Reed-Solomon encoder receiving an output of the front end component, the front end component outputting a substantially continuous stream of data to the RS (Reed-Solomon) Encoder, wherein if a video data rate to the front end component is insufficient to satisfy the RS Encoder, null words are generated by the front end component such that the RS Encoder is never starved for data.

4. The system of claim 2, comprising a forward error correcting component receiving data from the front end component.

5. The system of claim 4, comprising a scrambler receiving data from the forward error correcting component and randomizing the data.

6. The system of claim 5, comprising a header generator periodically outputting a header, a first portion of which includes preset data useful for synchronizing a receiver, a second portion of which includes variable data including control information useful by the receiver, each header being associated with a unit of multimedia data from the scrambler.

7. The system of claim 6, comprising a differential encoder representing absolute data from the header generator as phase shifted quadrature data.

8. The system of claim 2, wherein the front end component combines four 25-bit values to form a single 100-bit word and then converts the 100-bit word into five 20-bit words.

9. The system of claim 2, wherein the system is implemented by an FPGA configured for preparing the HDMI and/or DVI data for wireless transmission in the 60 GHz band.

19. The system of claim 2, in combination with a receive digital processing system for wireless reception of the HDMI and/or DVI data, the receive digital processing system deserializing received data using a deserializer aligning data by using a first character of a received header to perform alignment in both I and Q channels.

10. A receive digital processing system for wireless reception of HDMI and/or DVI data, the system deserializing received data using a deserializer aligning data by using a first character of a received header to perform alignment in both I and Q channels.

11. The system of claim 10, wherein the deserializer bonds parallel I and Q data by aligning them relative to each other.

12. The system of claim 10, comprising a descrambler receiving data from the deserializer.

13. The system of claim 12, comprising a forward error correction decoder receiving data from the descrambler.

14. The system of claim 13, comprising a back end component receiving data from the decoder and extracting original video and control data therefrom.

15. The system of claim 14, wherein the back end component is caused to strip every nth word if it is a null word, the nth word being discarded along with the following n−

1 words and otherwise the n words being assembled into a 100-bit word.

16. The system of claim 15, wherein the back end component separates each 100-bit word into four 25-bit words.

17. The system of claim 16, wherein if the most significant bit of a 25-bit word is a first binary value, the remaining 24 bits are output as video data, and otherwise the remaining 24 bits are output as control data and/or ancillary data.

18. The system of claim 10, wherein the system is implemented by an FPGA configured for processing the HDMI and/or DVI data received from wireless transmission in the 60 GHz band.

20. The system of claim 10, in combination with a transmit digital processing system for wireless transmission of HDMI and/or DVI data, the transmit digital processing system converting the data into two data streams, wherein the system includes a front end component multiplexing video data with control data.