Method for treating base oxide to improve high-K material deposition

• US 20060094192A1
• Filed: 01/31/2005
• Published: 05/04/2006
• Est. Priority Date: 10/29/2004
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shih-Chang, Yao, Liang-Gei, Yang, Ming-Ho
• Application Number:
  US11/048,487
• Publication Number:
  US 20060094192A1
• Time in Patent Office: Days
• US Class Current: 438/287
• CPC Class Codes: C23C 16/0227 by cleaning or etching
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02307 treatment by exposure to a liquid
• CPC Class Codes: H01L 21/02312 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/02315 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for forming a high-K material layer in a semiconductor device fabrication process including providing a silicon semiconductor substrate or thermally growing interfacial oxide layer comprising silicon dioxide over the silicon substrate; treating with an aqueous base solution or nitridation and depositing a high-K material layer.

Claims

1. A method for forming a high-K material layer in a semiconductor device fabrication process comprising the steps of:

providing a substrate;

treating said substrate with an aqueous basic solution; and

,

depositing at least one high-K material layer over said substrate.

2. The method of claim 1, wherein said substrate is a silicon substrate or an interfacial oxide layer.

3. The method of claim 2, wherein the basic solution comprises any kind of solution which can provide —

OH.

4. The method of claim 2, wherein the basic solution containing solution further comprises at least one of H₂O₂ and HCl.

5. The method of claim 2, wherein the interfacial oxide layer is grown to a thickness of about 5 Angstroms to about 100 Angstroms.

6. The method of claim 2, wherein the step of depositing at least one high-K material layer comprises an atomic layer chemical vapor deposition (ALCVD) method.

14. The method of claim 2, wherein the interfacial oxide layer is grown to a thickness of about 5 Angstroms to about 100 Angstroms.

15. The method of claim 2, wherein the step of depositing at least one high-K material layer comprises an atomic layer chemical vapor deposition (ALCVD) method.

7. A method for forming a high-K material layer in a semiconductor device fabrication process comprising the steps of:

providing a substrate;

performing a nitridation step over said substrate; and

depositing at least one high-K material layer.

8. The method of claim 7, wherein said substrate is a silicon substrate or an interfacial oxide layer.

9. The method of claim 7, wherein said nitridation step is selected from the group consisting of an annealing in an NO containing ambient, annealing in an NH₃ containing ambient, and annealing in an NO/NH₃ mixture containing ambient.

10. The method of claim 7, wherein said nitridation step is a plasma treatment having a plasma source gas selected from the group consisting of nitrogen (N₂), ammonia (NH₃), and a mixture thereof.

11. The method of claim 7, wherein the nitridation step is carried out at a temperature from about 0°

C. to about 1200°

C.

12. The method of claim 8, wherein the interfacial oxide layer is grown to a thickness of about 5 Angstroms to about 100 Angstroms.

13. A method for forming a high-K dielectric layer stack in a semiconductor device fabrication process comprising the steps of:

providing a silicon semiconductor substrate;

growing an interfacial oxide layer comprising silicon dioxide over the silicon substrate;

carrying out a nitridation step oversaid interfacial oxide layer selected from the group consisting of annealing in an ambient comprising at least one of NO and NH₃, and plasma treating in an ambient comprising at least one of N₂ and NH₃. and,

depositing a high-K material layer stack comprising a lowermost hafnium oxide (HfO₂) layer over said interfacial oxide layer.