Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology

• US 20060094194A1
• Filed: 11/04/2004
• Published: 05/04/2006
• Est. Priority Date: 11/04/2004
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Tze-Liang, Chen, Shih-Chang, Chen, Chien-Hao, Chen, Chia-Lin
• Application Number:
  US10/982,115
• Publication Number:
  US 20060094194A1
• Time in Patent Office: Days
• US Class Current: 438/301
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method of forming a semiconductor device comprises providing a gate electrode having exposed side walls formed in a substrate, forming dummy spacers on the gate electrode exposed side walls, performing a first implant to form source and drain implants, forming a capping layer over the gate electrode, the dummy sidewall spacers, and the source and drain, performing a first anneal, and removing the capping layer and the dummy sidewall spacers.

Claims

1. A method of forming a semiconductor device, comprising:

providing a gate electrode formed in a substrate, having exposed side walls;

forming dummy spacers on the gate electrode exposed side walls;

performing a first implant to form source and drain;

forming a capping layer over the structure, the dummy sidewall spacers, and the source and drain;

performing a first anneal; and

removing the capping layer and the dummy sidewall spacers.

2. The method of claim 1 further comprising:

performing a second implant to form low doped drain implants after removing the capping layer and the dummy sidewall spacers; and

performing a second anneal after performing the second implant.

3. The method of claim 1 further comprising forming another implant before forming dummy spacers and after providing the gate electrode.

4. The method of claim 1 further comprising forming final sidewall spacers on the gate electrode exposed side walls to form the semiconductor device.

5. The method of claim 1 wherein the semiconductor device includes a junction having a depth between about 5 nm and about 50 nm.

6. The method of claim 1 wherein the dummy spacers and the capping layer are each formed at a temperature of less than about 600°

C.

7. The method of claim 1 wherein the dummy spacers and the capping layer are each formed at a temperature between about 350°

C. and 600°

C.

8. The method of claim 1 wherein the dummy spacers and the capping layer comprises silicon nitride or silicon nitride/silicon oxide stack.

9. The method of claim 1 wherein the dummy spacers and the capping layer each have a stress between about −

2 Gpa and about 2 Gpa.

10. The method of claim 1 wherein the dummy spacers and the capping layer each have a stress between about 0.5 Gpa and about 1.5 Gpa.

11. The method of claim 1 wherein the dummy spacers are removed at an etch rate between about 3 nm and about 100 nm per minute using about 1% hydrofluoric acid (HF) at about room temperature.

12. The method of claim 1 wherein the dummy spacers are removed at an etch rate between about 5 nm and about 80 nm per minute using about 1% HF at about room temperature.

13. The method of claim 1 wherein the dummy spacers has an etch rate between about 3 nm and about 100 nm per minute in 1% HF solution and at about room temperature;

the capping layer has an etch rate between about 30 nm and about 1000 nm per minute in 1% HF solution and at about room temperature.

14. The method of claim 1 wherein the first anneal is conducted at a temperature of from about 800 to 1200°

C. and the second anneal is conducted at a temperature of from about 600 to 1100°

C.

15. A method of forming a semiconductor device, comprising:

providing a gate electrode having exposed side walls;

performing a first implant to form first low doped drain implants adjacent and outboard of the gate electrode;

forming dummy spacers on the gate electrode exposed side walls;

performing a second implant to form source and drain;

forming a capping layer over the gate electrode, the dummy sidewall spacers and the gate electrode;

performing a first anneal;

removing the capping layer and the dummy sidewall spacers;

performing a third implant to form second low doped drain implants;

performing a second anneal; and

forming final sidewall spacers on the gate electrode exposed side walls to form the semiconductor device, having a junction having a depth ranging from about 5 nm to about 50 nm.

16. The method of claim 15, wherein the dummy spacers and the capping layer each comprises silicon nitride formed at a temperature of less than about 600°

C.

17. The method of claim 15, wherein the dummy spacers comprise silicon nitride of silicon nitride or a silicon nitride/silicon oxide stack.

18. The method of claim 15, wherein the dummy spacers and the capping layer each have a stress of from about −

2 G to about 2 Gpa.

19. The method of claim 15, wherein the dummy spacers are removed at an etch rate of from about 3 nm to about 100 nm per minute using about 1% HF at about room temperature.

20. The method of claim 15, wherein:

the dummy sidewall spacers has an about 1.0% HF etch rate of from about 3 nm to 100 nm/minute at about room temperature;

the capping layer has an about 1.0% HF etch rate of from about 30 to 1000 Å

/minute at about room temperature;

and the final sidewall spacers have an HF rate of from about 5.0 to 200.0 Å

/minutes.

21. The method of claim 15, wherein the first anneal is conducted at a temperature of from about 800°

C. to about 1200°

C. and the second anneal is conducted at a temperature of from about 600°

C. to about 1100°

C.

22. A method of forming a metal-oxide-semiconductor (MOS) device, comprising the steps of:

providing a gate electrode having exposed side walls;

performing a first implant to form first low doped drain implants;

forming dummy spacers on the gate electrode exposed side walls, wherein the dummy sidewall spacers have an about 1.0% HF etch rate of from about 3 m to 100 nm/minute at about room temperature;

performing a second implant to form source and drain;

forming a capping layer over the gate electrode, the dummy sidewall spacers, and the source and drain;

the capping layer having an about 1.0% HF etch rate of from about 30 to about 1000 Å

/minute at about room temperature;

performing a first anneal;

removing the capping layer and the dummy sidewall spacers;

performing a third implant to form second low doped drain implants;

performing a second anneal; and

forming final sidewall spacers on the gate electrode exposed side walls to for the MOS device;

the final sidewall spacers having an HF rate from about 5.0 to 200.0 Å

/minutes.

23. The method of claim 22, wherein the MOS device includes a junction having a depth of from about 5 to 50 nm.

24. The method of claim 22, wherein the dummy spacers comprise silicon nitride or a silicon nitride/silicon oxide stack.

25. The method of claim 22, wherein the dummy spacers have a stress of from about −

2 Gpa to about 2 Gpa.

26. The method of claim 22, wherein the first anneal is conducted at a temperature of from about 800°

C. to about 1200°

C. and the second anneal is conducted at a temperature of from about 600°

C. to about 1100°

C.