Method and apparatus for controlling variable delays in electronic circuitry

• US 20060095221A1
• Filed: 11/03/2004
• Published: 05/04/2006
• Est. Priority Date: 11/03/2004
• Status: Abandoned Application

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Salmi, Jacob Alvin, Repucci, Thomas A.
• Application Number:
  US10/980,578
• Publication Number:
  US 20060095221A1
• Time in Patent Office: Days
• US Class Current: 702/106
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24

Abstract

A circuit with delay compensation for variable delays, such as those caused by environmental conditions. A delay compensation element having a delay pattern that matches the delay pattern of the circuit to be compensated is included in the feedback path of a phase locked loop. The delay compensation is described as a programmable delay, which has a rate of change in relation to temperature that varies with the programmed value of the delay. Such a circuit is used in a channel of automatic test equipment. The delay element is incorporated in the feedback path of a phase locked loop used in a clock generation circuit. The structure provides for edge placement accuracies below 250 picoseconds, even if CMOS components are used in the channel.

Claims

1. A delay compensated electronic system comprising:

a) a first circuit having a delay dependency on at least one environmental variable;

b) a second circuit having a feedback path, the second circuit connected in series with the first circuit; and

c) a delay compensation element connected in the feedback path having a delay dependency proportional to the delay dependency of the first circuit.

2. The delay compensated electronic system of claim 1 wherein the delay compensation element comprises a programmable delay circuit.

3. The delay compensated electronic system of claim 2 wherein the programmable delay of the delay compensation element is programmed with a value to yield a rate of change of delay with respect to temperature comparable to the delay dependency of the first circuit.

4. The delay compensated electronic system of claim 1 wherein the delay dependency of the first circuit is a change of delay with respect to temperature and the delay of the delay compensation element has a corresponding change of delay with respect to temperature.

5. The delay compensated electronic system of claim 4 wherein the second circuit comprises a phase locked loop.

6. The delay compensated electronic system of claim 5 wherein the phase locked loop comprises a voltage controlled oscillator and a phase detector and a feedback path between the voltage controlled oscillator and the phase detector and the delay compensation element is connected in the path between the voltage controlled oscillator and the phase detector.

7. The delay compensated electronic system of claim 6 wherein the first circuit comprises a DDS circuit.

8. The delay compensated electronic system of claim 7 wherein the DDS circuit comprises a CMOS digital to analog converter.

9. The delay compensated electronic system of claim 1 wherein the first circuit comprises CMOS circuitry having a delay that varies with temperature.

10. An automatic test system having a plurality of channels, each channel comprising:

a) at least one first circuit having a first delay that changes in response to temperature with a first pattern;

b) a phase locked loop having a feedback path coupled to the at least one first circuit; and

c) a delay element having a delay that changes in response to temperature with the first pattern, the delay element connected in the feedback path.

11. The automatic test system of claim 10 wherein the phase locked loop comprises a second order phase detector.

12. The automatic test system of claim 11 wherein the at least one first circuit comprises a digital to analog converter.

13. The automatic test system of claim 10 wherein each channel comprises a clock generator and the at least one first circuit and the phase locked loop are portions of the clock generator.

14. The automatic test system of claim 10 wherein each channel comprises calibration circuitry.

15. The automatic test system of claim 10 wherein the at least one first circuit comprises a digital to analog converter.

16. The automatic test system of claim 15 wherein the digital to analog converter comprises a CMOS digital to analog converter.

17. The automatic test system of claim 16 wherein the delay element comprises a programmable CMOS delay element.

18. The automatic test system of claim 10 wherein the delay element comprises a programmable delay element.

19. A method of operating a circuit having one or more sub-circuits that have a delay that changes in response to environmental conditions with a first pattern, comprising:

a) providing a delay element in a feedback path in the circuit, the delay element having a delay that changes in response to environmental conditions with the first pattern; and

b) operating the circuit.

20. The method of operating a circuit of claim 19 wherein the circuit is in a channel of an automatic test system.

21. The method of operating a circuit of claim 20 wherein providing a delay element comprises:

a) providing a programmable delay element;

b) setting the programmed delay value of the delay element;

c) after the programmed delay value of the delay element is set, calibrating for fixed delay in the tester channel.

22. A method of manufacturing semiconductor devices using the method of claim 21, wherein operating the circuit comprises performing a test on at least one semiconductor device during its manufacture and the method further comprises making a change in the manufacturing process as a result of the result of the test.

23. The method of manufacturing semiconductor devices of claim 22 wherein the first pattern is a rate of change of delay with respect to temperature and providing a delay element having a delay that changes in response to environmental conditions with the first pattern comprises providing a delay element that has a rate of change of delay with respect to temperature matching the first pattern.

24. The method of claim 19 wherein the providing a delay element comprises providing a variable delay with the delay set to have a change in delay as a function of temperature that matches the first pattern.

25. The method of claim 24 wherein the circuit is a channel of an automatic test system having a plurality of channels, the method additionally comprising calibrating the automatic test system for differences in fixed delay between the channels.

26. The method of operating a circuit of claim 19 wherein the one or more sub-circuits comprise a DDS circuit.

27. The method of claim 26 wherein operating the circuit comprises generating a stable clock signal.