System and method for improved memory performance in a mobile device

• US 20060095622A1
• Filed: 10/28/2004
• Published: 05/04/2006
• Est. Priority Date: 10/28/2004
• Status: Abandoned Application

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Rosner, Stephan, Gershon, Eugen, McClain, Mark
• Application Number:
  US10/975,629
• Publication Number:
  US 20060095622A1
• Time in Patent Office: Days
• US Class Current: 710/107
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method are disclosed for improved memory performance in a mobile device. A mobile device incorporating teachings disclosed herein may include, for example, a central processing unit (CPU) residing on a first chip. The mobile device may also include a memory system residing on a second chip. The memory system may include, for example, a memory controller and at least one type of memory combined in a single multi-chip package. The multi-chip package may effectively internalize higher pin count interfaces interconnecting the memory controller and the at least one type of memory. With some implementations, a high frequency, low pin-count external bus may form at least a portion of a link communicatively coupling the multi-chip package and the CPU. In practice, the high frequency, low pin-count external bus may physically connect to a bus interface residing on the first chip. The bus interface may be communicatively coupled to the CPU via an internal CPU bus also located on the first chip. In operation, the bus interface may provide bus translation between the high frequency, low pin-count external bus, and the internal CPU bus.

Claims

1. A method of improved memory access comprising:

recognizing a need to access a memory;

initiating communication of a memory command via an internal bus located on a first chip;

receiving the memory command at a bus interface located on the first chip;

translating the memory command to facilitate communication via an external bus;

receiving a translated memory command at a memory controller via the external bus, the memory controller located on a different chip; and

accessing the memory from the memory controller via an internalized bus having a width of at least 32 bits to perform an operation indicated by the translated memory command, the internalized bus included within a multi-chip package.

2. The method of claim 1, wherein the external bus comprises a high frequency, low pin-count bus.

3. The method of claim 1, wherein the memory comprises a dynamic memory.

4. The method of claim 1, wherein the memory comprises DRAM.

5. The method of claim 1, wherein the memory is selected from a group consisting of SDRAM, DDRAM, NOR Flash, and DDR.

6. The method of claim 1, wherein the internalized bus has a width of 64 bits.

7. The method of claim 1, wherein a central processing unit located on the first chip initiates communication of the memory command.

8. The method of claim 1, further comprising:

recognizing a new need to access a different memory;

initiating communication of a new memory command via the internal bus located on the first chip;

receiving the new memory command at the bus interface located on the first chip;

translating the new memory command to facilitate communication via the external bus;

receiving the translated new memory command at the memory controller via the external bus; and

accessing the different memory from the memory controller.

9. The method of claim 8, further comprising creating a local copy in the different memory of information located in the memory without accessing the internal bus.

10. The method of claim 8, further comprising locating the memory controller, the memory, and the different memory in a top package of the multi-chip package.

11. The method of claim 1, further comprising operating the external bus at 200 MHz.

12. The method of claim 1, further comprising applying low-voltage differential signaling across the external bus.

13. The method of claim 10, further comprising securing the multi-chip package within an interior cavity of a mobile device.

14. The method of claim 13, wherein the interior cavity is at least partially formed by a housing component of a wireless telephonic device.

15. A method of improving memory operation in a mobile device, comprising:

forming a memory subsystem module that comprises a memory controller and a dynamic memory;

collapsing the pin count necessary to interconnect the memory controller and the dynamic memory into a collection of internalized interconnects included within a multi-chip package;

using a low pin count external bus to form at least a portion of a communication path interconnecting the memory controller of the memory subsystem with a central processing unit located on a different chip; and

forming the different chip and the memory subsystem for location within the mobile device.

16. The method of claim 15, further comprising defining a mechanical interface for the memory subsystem that supports locating a package containing the memory subsystem as a top package in a multi-chip package.

17. The method of claim 15, further comprising booting the mobile device using information located in the memory subsystem.

18. A mobile device memory system, comprising:

a central processing unit (CPU) for a mobile device residing on a first chip;

a modular memory system residing off the first chip and in a multi-chip package, the modular memory system comprising a memory controller interconnected with at least one type of memory via interfaces internalized within a package; and

a high frequency, low pin-count external bus forming at least a portion of a link communicatively coupling the memory controller and the CPU.

19. The system of claim 18, further comprising a bus interface residing on the first chip, the bus interface being communicatively coupled to both the external bus and an internal CPU bus also located on the first chip.

20. The system of claim 19, wherein the at least one type of memory is selected from a group consisting of a NOR Flash type, an SDRAM type, an SRAM type, and a DDR type.

21. The system of claim 20, further comprising a 64 bit wide data bus internalized within the multi-chip package and interconnecting the memory controller with the at least one type of memory.

22. The system of claim 21, further comprising an application processor communicatively coupled to the internal CPU bus.

23. The system of claim 22, further comprising a housing component of a mobile device, the housing component at least partially forming an internal cavity housing the first chip and the multi-chip package.

24. The system of claim 18, wherein the first chip does not contain NOR Flash type memory, SDRAM type memory, SRAM type memory, or DDR type memory.

25. A system for improved memory performance in a mobile device, comprising:

a multi-chip package having a package on package configuration;

a first package of the multi-chip package comprising a baseband controller, the baseband controller having at least one core processor,

a second package of the multi-chip package comprising a memory subsystem, the memory subsystem having at least one type of memory and a memory controller; and

an interconnection mechanism forming at least a portion of a communication link interconnecting the at least one core processor and the memory controller.

26. The system of claim 25, further comprising a second core processor, wherein the second core processor comprises a Digital Signal Processing core processor.

27. The system of claim 25, wherein the interconnection mechanism comprises a low pin-count external bus.

28. The system of claim 25, wherein the first package resides at a layer of the multi-chip package that is lower than a second package layer.

29. The system of claim 25, further comprising a bus interconnecting the at least one type of memory and the memory controller, wherein the bus has a width of at least 64 bits.

30. The system of claim 25, further comprising a cellular telephone, wherein the cellular telephone comprises a display and the multi-chip package.

31. The system of claim 25, further comprising a cellular telephone, wherein the cellular telephone comprises a display, a keypad, an MP3 player, a local area wireless transceiver, a wide area wireless transceiver, and the multi-chip package.