Method and apparatus for pushing data into a processor cache

• US 20060095679A1
• Filed: 10/28/2004
• Published: 05/04/2006
• Est. Priority Date: 10/28/2004
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Edirisooriya, Samantha J.
• Application Number:
  US10/977,830
• Publication Number:
  US 20060095679A1
• Time in Patent Office: Days
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch

Abstract

An arrangement is provided for using a centralized pushing mechanism to actively push data into a processor cache in a computing system with at least one processor. Each processor may comprise one or more processing units, each of which may be associated with a cache. The centralized pushing mechanism may predict data requests of each processing unit in the computing system based on each processing unit'"'"'s memory access pattern. Data predicted to be requested by a processing unit may be moved from a memory to the centralized pushing mechanism which then sends the data to the requesting processing unit. A cache coherency protocol in the computing system may help maintain the coherency among all caches in the system when the data is placed into a cache of the requesting processing unit.

Claims

1. An apparatus for pushing data from a memory into a cache of a processing unit in a computing system, comprising:

request prediction logic to analyze memory access patterns by the processing unit and to predict data requests of the processing unit based on the memory access patterns; and

push logic to issue a push request per cache line of data predicted to be requested by the processing unit, and to send the cache line associated with the push request to the processing unit if the processing unit accepts the push request, the processing unit placing the cache line in the cache.

2. The apparatus of claim 1, further comprising a prefetch data buffer to temporarily store the data predicted to be requested by the processing unit, the data retrieved from the memory.

3. The apparatus of claim 1, wherein the computing system comprises at least one processor, each processor including at least one processing unit.

4. The apparatus of claim 1, wherein the request prediction logic analyzes memory access patterns by each processing unit in the computing system and to predict data requests of each processing unit based on the memory access patterns;

and the push logic pushes data predicted to be requested by each processing unit to a cache of a targeted processing unit.

5. The apparatus of claim 1, wherein the computing system comprises a coherency protocol to ensure coherency among caches in the computing system when the request cache line is placed in the cache of the processing unit.

6. A computing system, comprising:

at least one processor, each processor including at least one processing unit associated with a cache;

at least one memory to store data accessible by each processing unit in the system; and

a centralized pushing mechanism to facilitate data traffic to and from the at least one memory, to predict data requests of each processing unit in the system, and to actively push data into a cache of a targeted processing unit in the at least one processor based on the predicted data requests of the targeted processing unit.

7. The computing system of claim 6, wherein a processing unit has faster access to data in a cache associated with the processing unit than to data in the at least one memory.

8. The computing system of claim 6, further comprising a cache coherency protocol to ensure coherency among caches in the computing system when the data predicted to be requested by the targeted cache is placed in the cache.

9. The computing system of claim 6, wherein the centralized pushing mechanism comprises:

request prediction logic to analyze memory access patterns by each processing unit in the system and to predict data requests of each processing unit based on the memory access patterns; and

push logic to issue a push request per cache line of data predicted to be requested by a processing unit, and to send the cache line associated with the push request to the processing unit if the processing unit accepts the push request.

10. The computing system of claim 9, further comprising a prefetch data buffer to temporarily store data predicted to be requested by a processing unit before the data is sent to the processing unit, the data retrieved from the memory.

11. The computing system of claim 6, wherein the at least one processor and the centralized pushing mechanism are coupled to a bus, the centralized pushing mechanism sending data to the targeted processing unit through bus write transactions.

12. The computing system of claim 11, wherein the bus comprises a push functionality and a cache line write transaction, the push functionality enabled during the cache line write transaction when the centralized pushing mechanism sends a cache line to a targeted processing unit through a cache line write transaction, wherein a cache line write transaction comprises an identification of the targeted processing unit.

13. The computing system of claim 12, wherein a cache line sent through a cache line write transaction is claimed by a processing unit whose identification matches the identification of the targeted processing unit in the transaction.

14. The computing system of claim 6, wherein the centralized pushing mechanism is a memory controller.

15. A method for using a centralized pushing mechanism to push data into a processor cache, comprising:

analyzing a memory access pattern by a processor;

predicting data requests of the processor based on the processor'"'"'s memory access pattern;

issuing a push request for data predicted to be requested by the processor; and

pushing the data into a cache of the processor.

16. The method of claim 15, further comprising moving the data from a memory to a buffer in the centralized pushing mechanism before issuing the push request.

17. The method of claim 15, further comprising ensuring cache coherency when pushing the data into the cache of the processor.

18. The method of claim 15, wherein issuing the push request comprises issuing a push request for each cache line of the data predicted to be requested by the processor.

19. The method of claim 18, wherein pushing a cache line of data comprises:

determining if the processor accepts the push request;

if the processor accepts the push request,

sending the cache line to the processor as a bus transaction, and

claiming the cache line from the bus by the processor; and

otherwise,

retrying to issue the push request.

20. The method of claim 19, further comprising handling the cache line claimed from the bus to ensure cache coherency.

21. The method of claim 19, wherein sending the cache line to the processor as a bus transaction comprises using a cache line write transaction of the bus and enabling a push functionality of the cache line write transaction.

22. A method for using a centralized pushing mechanism to push data into a cache of a processing unit, comprising:

analyzing memory access patterns by each processing unit in a plurality of processors, each processor including at least one processing unit;

predicting data requests of each processing unit based on each processing unit'"'"'s memory access pattern;

issuing at least one push request for data predicted to be requested by each processing unit; and

pushing data predicted to be requested by a processing unit into a cache of the processing unit.

23. The method of claim 22, wherein predicting data requests comprises predicting a common data request among multiple processing units in the plurality of processors.

24. The method of claim 22, further comprising moving the data predicted to be requested by each processing unit from a memory to a buffer in the centralized pushing unit before issuing the at least one push request.

25. The method of claim 22, wherein issuing the at least one push request comprises issuing a push request per each cache line of the data predicted to be requested by each processing unit, the push request including an identification of a targeted processing unit.

26. The method of claim 25, wherein pushing a cache line of data to a cache of a targeted processing unit comprises:

determining if the targeted processing unit accepts the push request;

if the targeted processing unit accepts the push request,

sending the cache line to the plurality of processors as a bus transaction, the bus transaction including an identification of a processing unit to which the cache line is sent, and

claiming the cache line from the bus by the targeted processor if the targeted processor'"'"'s identification matches the identification of the processor to which the cache line is sent; and

otherwise,

retrying to issue the push request.

27. The method of claim 26, wherein sending the cache line to the plurality of processors as a bus transaction comprises using a cache line write transaction of the bus and enabling a push functionality of the cache line write transaction.

28. The method of claim 26, further comprising handling the claimed cache line to ensure coherency among caches of all processing units in the plurality of processors.

29. An article comprising a machine readable medium that stores data representing a centralized pushing mechanism comprising:

request prediction logic to analyze memory access patterns by at least one processing unit in a computing system and to predict data requests of the at least one processing unit based on the memory access patterns;

a prefetch data buffer to temporarily store data predicted to be requested by the at least one processing unit, the data retrieved from a memory; and

push logic to issue a push request per cache line of data predicted to be requested by the at least one processing unit, and to send the cache line associated with the push request to a targeted processing unit if the targeted processing unit accepts the push request, the targeted processing unit placing the cache line in the cache.

30. The article of claim 29, wherein the data representing the computing system comprises a hardware description language code.

31. The article of claim 29, wherein the data representing the computing system comprises data representing a plurality of mask layers string physical data representing the presence or absence of material at various locations of each of the plurality of mask layers.

32. An article comprising a machine readable medium having stored thereon data which, when accessed by a processor in conjunction with simulation routines, provides functionality of a centralized pushing mechanism including:

request prediction logic to analyze memory access patterns by at least one processing unit in a computing system and to predict data requests of the at least one processing unit based on the memory access patterns;

a prefetch data buffer to temporarily store data predicted to be requested by the at least one processing unit, the data retrieved from a memory; and

push logic to issue a push request per cache line of data predicted to be requested by the at least one processing unit, and to send the cache line associated with the push request to a targeted processing unit if the targeted processing unit accepts the push request, the targeted processing unit placing the cache line in the cache.

33. The article of claim 32, wherein the centralized pushing mechanism facilitates data traffic to and from a memory, and to actively push data into a cache of a targeted processing unit, the targeted processing unit having more efficient access to data in the cache than access to data in the memory.