Programmable control interface device

• US 20060095692A1
• Filed: 09/01/2005
• Published: 05/04/2006
• Est. Priority Date: 09/03/2004
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Chalopin, Herve, Tabaries, Laurent
• Granted Patent: US 7,600,068 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G05B 19/045 using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
• CPC Class Codes: G05B 2219/23277 Use of separate interface software, main program calls functions from it
• CPC Class Codes: G05B 2219/25451 Connect module to bus using interface with adaptive logic
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

A programmable control interface is for circuits using complex commands. The programmable interface includes a memory for storing sampled commands and a sequencing circuit. The sequencing circuit is programmable. Thus, a processor downloads into the programmable interface a sequencing specific to the sequence of commands. Once the programmable interface has been programmed, the processor launches the start of the sequence and the programmable interface manages and controls in a standalone manner the inputs/outputs with the slave circuit. The management and control of the slave circuit is independent of any interrupt specific to the system. The programmable interface uses a software-type upgrade to interface with new slave circuits that may appear on the market.

Claims

1. A programmable interface device for controlling a slave circuit, wherein any control signal intended to control the slave circuit is previously decomposed into a succession of bits, the succession corresponding to a sampling of the signal with the aid of a sampling signal, a period of which is at most equal to the smallest duration between two changes of state of the control signal, said device comprising:

a first memory for storing the sampled control signal;

a first address counter for supplying addresses to said first memory; and

a programmable state machine for driving the first memory and the first address counter.

2. The device according to claim 1 wherein the first memory is designed to store, furthermore, addresses destined for the slave circuit.

3. The device according to claim 1 wherein the first memory is designed, furthermore, to store control words destined for the slave circuit.

4. The device according to claim 1, further comprising:

a second memory for storing data destined for, and originating from, the slave circuit; and

a second address counter for supplying addresses to said second memory, the second address counter being driven by the programmable state machine.

5. The device according to claim 4 wherein the second memory is designed, furthermore, to store addresses destined for the slave circuit.

6. The device according to claim 4 wherein the second memory is designed, furthermore, to store control words destined for the slave circuit.

7. The device according to claim 4 wherein the state machine comprises:

a state memory whose content corresponds to commands and addresses destined for the first and second memories and the first and second address counters;

a state counter which serves to address the state memory; and

a programmable clock with a minimum frequency, the minimum frequency being greater than a frequency of the sampling signal.

8. The device according to claim 7 wherein the state machine further comprises at least one loop counter for counting the number of times that a line sequence of the state memory is read repeatedly.

9. The device according to claim 7 wherein the state machine further comprises:

an input for receiving an availability signal originating from the slave circuit; and

means of neutralization of the programmable clock for halting the programmable clock in response to the availability signal when the availability signal indicates the unavailability of the slave circuit.

10. The device according to claim 4, further comprising at least one multiplexing means for multiplexing at least one data output of the first memory with at least one input/output of the second memory.

11. The device according to claim 4, wherein the slave circuit is a programmable ROM device.

12. The device according to claim 11, wherein the ROM device comprises:

a command bus configured to supply read and write commands to the slave circuit; and

a data bus configured to serve as an address bus and as a command bus for complex commands.

13. The device according to claim 1 wherein the device is configured as an integrated circuit.

14. An electronic system comprising:

a central processor furnished with a central bus for exchanging data, addresses and commands with other circuits;

a command bank memory storing at least one set of complex instructions corresponding to at least one slave circuit, the memory being coupled to the central bus; and

a programmable interface device coupled to the central bus for controlling the at least one slave circuit, the interface device including;

a first memory for storing the complex instructions,

a first address counter for supplying addresses to said first memory, and

a programmable state machine for driving the first memory and the first address counter.

15. The system according to claim 14, wherein said system is configured as an on-chip system.

16. A method of control of a slave circuit by a system with a central processor with the aid of a programmable control interface device, wherein any control signal, intended to control the slave circuit, is decomposed into a succession of bits by sampling with the aid of a sampling signal, a period of said sampling signal being at most equal to the smallest duration between two changes of state of a control signal, the programmable control interface device including a first memory, a first address counter, and a programmable state machine, said method comprising the steps of:

computation by the processor of a series of sampled commands;

computation of a succession of states corresponding to the command series;

loading into the programmable control interface device the sampled command series and of the succession of states; and

after the loading step, supplying to the first memory and to the first counter, by the state machine, instructions for providing on an output bus signals intended for commanding the slave circuit.

17. The method according to claim 16, the programmable interface device further including a second memory and a second address counter, wherein said method further comprises the steps of:

prior to the step of supplying instructions, loading of data to be written into the slave circuit into the second memory; and

simultaneously with the step of supplying instructions to the first memory and to the first counter, supplying to the second memory and to the second counter, by the state machine, instructions for supplying on a data bus the data to be written.

18. The method according to claim 16, the programmable interface device further including a second memory and a second address counter, wherein said method further comprises the steps of:

simultaneously with the step of supplying instructions to the first memory and to the first counter, supplying to the second memory and to the second counter, by the state machine, instructions for making it possible to copy into the second memory data originating from a data bus of the slave circuit; and

after having copied the data, the state machine informing the processor that it can proceed with a transfer of the data from the second memory to another circuit.

19. The method of claim 16, wherein the series of sampled commands corresponds to the sampled control signal.

20. The method of claim 16, further comprising the step of generating the instructions from the sampled command series and succession of states.

21. A system comprising:

means for sampling a control signal to generate a series of sampled commands;

means for computing a succession of states corresponding to the series of sampled commands;

means for loading the sampled command series and succession of states into a programmable control interface device; and

means for generating instructions from the sampled command series and succession of states for controlling a slave circuit.