Multimedia system for a vehicle

• US 20060095756A1
• Filed: 07/01/2005
• Published: 05/04/2006
• Est. Priority Date: 07/01/2004
• Status: Active Grant

• Current Assignee: Harman Becker Automotive Systems GmbH (Samsung Electronics Co. Ltd.)
• Original Assignee: Harman Becker Automotive Systems GmbH (Samsung Electronics Co. Ltd.)
• Inventors: Rupprecht, Matthias, Erforth, Thomas
• Granted Patent: US 7,664,931 B2
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G01C 21/36 Input/output arrangements for on-board computers
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H04N 21/2146 located in mass transportation means, e.g. aircraft, train or bus flight-deck installations for entertainment or communications B64D11/0015; arrangements specially adapted for transportation systems in broadcast systems H04H20/62; moving wireless networks H04W84/005

Abstract

A scalable and fully configurable computing architecture for a mobile multimedia architecture used in a vehicle includes a head unit having a processor, a field programmable gate array and a memory. The processor and the memory are configured to communicate over a first bus that is a dedicated memory bus, and the processor and the field programmable gate array are configured to communicate over a separate second bus. The field programmable gate array is configured to be loaded from memory with part of a multimedia vehicle-related application-specific functionality that is executable by the field programmable gate array, and the processor is cooperatively operable with the field programmable gate array to execute another portion of the multimedia vehicle-related application-specific functionality. The multimedia vehicle-related application-specific functionality in the field programmable gate array may be changed with software and downloaded to the field programmable gate array in the field. In addition, due to the first and second busses being recognized industry standard busses, any of the processor, the field programmable gate array and the memory are fully scaleable and configurable.

Claims

1. A computing architecture for a mobile multimedia system used in a land-based vehicle comprised of a plurality of interconnected electrical components including at least one processor with a memory and a field programmable gate array connected with each other by a standardized data bus for the exchange of data between the components, wherein the field programmable gate array is adapted, upon system start-up or during system operation, to load data from the memory to realize application-specific functionality by logic functions implemented inside the field programmable gate array.

2. The computing architecture according to claim 1, where the field programmable gate array serves as a scaleable hardware interface between the central processor and peripheral components comprising at least two of an external memory, a display, a network, a mass storage, an input/output system controller and a peripheral input/output component.

3. The computing architecture according to claim 1, where time critical or computing intensive functions are realized by means of dedicated scalable hardware accelerators included in the field programmable gate array.

4. The computing architecture according to claim 1, where system functions that include graphic/video processing, DVD decoding or DSP functions are shared between the application software running on the central processor and the field programmable gate array in a way that the gate array performs pre- or post processing of I/O data.

5. The computing architecture according to claim 1, where time-critical or computing intensive functions are realized by means of dedicated hardware accelerators included in the field programmable gate array.

6. The computing architecture according to claim 1, where the at least one central processor comprises two central processors, and where high priority or real-time applications are assigned to one processor and lower priority applications are assigned to the other processor.

7. The computing architecture according to claim 6, where upon completion of the system start-up, an application may be transferred from one processor to another.

8. The computing architecture according to claim 1, where the memory comprises at least one of a random access memory or a flash memory, or combinations thereof.

9. The computing architecture according to claim 1, where the at least one central processor and the memory are integrated as a module.

10. The computing architecture according to claim 1, where the application-specific functionality includes at least one of DVD decoding, digital signal processing and graphic functions.

11. The computing architecture according to claim 1, where the field programmable gate array contains an embedded processor core to be used to implement a hardware accelerator.

12. A computing architecture for a mobile multimedia system used in a land-based vehicle, the computing architecture comprising:

a processor;

a field programmable gate array; and

a recognized industry standard communication bus configured to communicate data between the processor and the field programmable gate array;

where the field programmable gate array is configured to be loaded with a first part of a multimedia vehicle-related application-specific functionality that is cooperatively operable with a second part of the multimedia vehicle-related application-specific functionality that is executable with the processor.

13. The computing architecture of claim 12, further comprising a memory configured to store the multimedia vehicle-related application-specific functionality, the memory accessible by the processor to download the first part of the multimedia vehicle-related application-specific functionality over the recognized industry standard communication bus to the field programmable gate array.

14. The computing architecture of claim 12, where the first part of the multimedia vehicle-related application-specific functionality is executable by the field programmable gate array to decode at least one of video or audio information, or combinations thereof, and the processor is configured to further process the decoded at least one of video or audio information.

15. The computing architecture of claim 12, where the processor, the field programmable gate array, and the recognized industry standard communication bus are configured to operate as a head unit for a vehicle.

16. A computing architecture for a mobile multimedia system used in a land-based vehicle, the computing architecture comprising:

a processor having a bus communication module configured to communicate with a predefined industry standard protocol;

a field programmable gate array having a bus communication module configured to communicate with the predefined industry standard protocol; and

a communication bus coupled between the bus communication modules, the communication bus configured to communicate data between the processor and the field programmable gate array with the predefined industry standard protocol;

where the field programmable gate array is loadable on startup with a vehicle navigation component, a digital video decoder component and a digital data disc driver component;

and where the navigation component and the digital video decoder component are configured to use the same data disc driver component to enable access to data stored on a digital data disc.

17. The computing architecture of claim 16, where the field programmable gate array is configured to be loaded with a first part of a multimedia-related application-specific functionality that is cooperatively operable with a second part of the multimedia-related application-specific functionality that is executable with the processor.

18. The computing architecture of claim 16, further comprising a memory in communication with the processor over a recognized industry standard memory bus, wherein the memory is configured to store the vehicle navigation component, the digital video decoder component and the digital data disc driver component, which are downloadable to the field programmable gate array by the processor over the memory bus and then over the communication bus.

19. The computing architecture of claim 16, where the field programmable gate array is further loadable on startup with a graphics controller, and the navigation component and the digital video decoder component are configured to use the same the graphics controller to drive a display.

20. A computing architecture for a mobile multimedia system used in a land-based vehicle, the computing architecture comprising:

a vehicle head unit;

a predefined industry standard communication bus included in the vehicle head unit, where the predefined industry standard communication bus is configured to provide communication compatibility with products from different manufacturers;

at least one processor and at least one field programmable gate array installable in the vehicle head unit and configurable to communicate over the predefined industry standard communication bus; and

a memory configured to store instructions related to the operational functionality of the vehicle head unit that are selectively executable by the processor and downloadable to the field programmable gate array over the predefined industry standard communication bus for execution by the field programmable gate array.

21. The computing architecture of claim 20, where the processor is operable to access and download the instructions stored in memory to the field programmable gate array over the predefined industry standard communication bus.

22. The computing architecture of claim 20, where the instructions comprise a plurality of multimedia related applications in support of the operation of the vehicle head unit, where some of the applications are downloadable into the field programmable gate array for execution, some of the applications are executable with the processor and some of the applications are a combination of both.

23. The computing architecture of claim 20, where the instructions comprise instructions to provide the functionality of a navigation system and instructions to provide the functionality of a digital video device decoder.

24. The computing architecture of claim 20, where the memory is configured to communicate over a dedicated recognized industry standard memory bus to the processor, and the instructions that are downloadable to the field programmable gate array are communicatable over the dedicated recognized industry standard memory bus to the processor, and then over the predefined industry standard communication bus to the field programmable gate array.

25. A method of operating a computing architecture for a mobile multimedia navigation system used in a land-based vehicle, the method comprising:

energizing a processor and a field programmable gate array included in a head unit of a vehicle;

loading a first portion of a multimedia application supported by the head unit into the field programmable gate array;

executing the first portion of the multimedia application to pre-process data with the field programmable gate array;

communicating the pre-processed data from the field programmable gate array to the processor over a recognized industry standard communication bus;

executing a second portion of the specific application with the processor to further process the pre-processed data from the field programmable gate array;

communicating the data processed by the processor back to the field programmable gate array over the recognized industry standard communication bus; and

further executing with the field programmable gate array the first portion of the specific application to post process the data processed by the processor.

26. The method of claim 25, loading the first portion comprises the processor retrieving the first portion of the multimedia application from a memory over a dedicated recognized industry standard memory bus.

27. The method of claim 26, where loading the first portion comprises the processor transmitting the first portion of the multimedia application retrieved from the memory to the field programmable gate array over the recognized industry standard communication bus.

28. A method of operating a computing architecture for a mobile multimedia navigation system used in a land-based vehicle, the method comprising:

providing a recognized industry standard communication bus protocol;

implementing operation of a first processor from a first processor manufacturer and a field programmable gate array in a head unit of a vehicle;

enabling communication between the first processor and the first field programmable gate array via the recognized industry standard communication bus;

implementing operation of a second processor from a second processor manufacturer to support the vehicle-related functionality provided by the head unit; and

enabling communication between the second processor, the first processor and the first field programmable gate array via the recognized industry standard communication bus.

29. The method of claim 28, where the field programmable gate array is a first field programmable gate array from a first field programmable gate array manufacturer and the method further comprises implementing operation in the head unit a second field programmable gate array from a second field programmable gate array manufacturer and enabling communication between the first processor, the second processor, the first programmable gate array and the second programmable gate array via the recognized industry standard communication bus.