System and method for automatic masking of compressed scan chains with unbalanced lengths
First Claim
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1. A method of performing scan test in a scan test architecture including at least one unbalanced scan chain including flip-flops, the method comprising the steps of:
- incrementing a count;
comparing the count to a value representing the flip-flops in the at least one unbalanced scan chain; and
performing masking in response to comparing the count to the value representing the flip-flops in the at least one unbalanced scan chain.
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Abstract
A scan test architecture is implemented. The scan test architecture provides a method of performing scan test of unbalanced scan chains. The scan test architecture generates a control signal (i.e., masking signal) to mask bits in an unbalanced scan chain. In one embodiment, the control signal is generated with a logic gate, a comparator, and a counter.
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Citations
15 Claims
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1. A method of performing scan test in a scan test architecture including at least one unbalanced scan chain including flip-flops, the method comprising the steps of:
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incrementing a count;
comparing the count to a value representing the flip-flops in the at least one unbalanced scan chain; and
performing masking in response to comparing the count to the value representing the flip-flops in the at least one unbalanced scan chain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A scan test system, comprising:
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an unbalanced scan chain segment including flip-flops storing a test pattern;
a counter generating a count;
a comparator coupled to the counter and generating a comparator output in response to comparing the count to a value associated with the flip-flops; and
a gate coupled to the unbalanced scan chain segment and coupled to the comparator, the gate generating an output in response to the test pattern and in response to the comparator output. - View Dependent Claims (11, 12, 13)
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14. A system comprising:
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a decompressor generating a test pattern;
a first unbalanced scan chain segment including first flip-flops, the first unbalanced scan chain segment coupled to the decompressor and storing first bits in response to the decompressor generating the test pattern;
a counter generating a count;
a first comparator coupled to the counter and generating a first comparator signal by comparing the count to a value representing the first flip-flops;
a first gate coupled to the first unbalanced scan chain segment and coupled to the first comparator, the first gate generating a first output in response to the first comparator signal; and
a compressor coupled to the first gate and generating a compressor output in response to the first output. - View Dependent Claims (15)
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Specification