Semiconductor memory chip, semiconductor memory module and method for transmitting write data to semiconductor memory chips

• US 20060095826A1
• Filed: 10/31/2005
• Published: 05/04/2006
• Est. Priority Date: 10/29/2004
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Wallner, Paul, Gregorius, Peter, Ruckerbauer, Hermann, Sichert, Christian, Savignac, Doninique
• Application Number:
  US11/261,911
• Publication Number:
  US 20060095826A1
• Time in Patent Office: Days
• US Class Current: 714/748
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A semiconductor memory module includes a plurality of semiconductor memory chips. Each semiconductor memory chip includes an interface circuit that is configured to detect a transmission error in a write datum and is further configured to output, via a separate signal path, a repeat request signal for the repeated transmission of the write datum detected as erroneous. This repeat request signal can be transmitted either as a single-bit signal or as a multibit signal (e.g., serially as an individual signal line to a superordinate memory controller).

Claims

1. A semiconductor memory chip comprising:

an interface circuit configured to receive write data and to detect a transmission error in the received write data, wherein, upon detection of a transmission error by the interface circuit, the interface circuit is further configured to output, via a request signal path, a repeat request signal for the repeated transmission of a write datum detected as erroneous.

2. The semiconductor memory chip of claim 1, wherein the interface circuit is configured to output the repeat request signal on an individual separate signal line.

3. The semiconductor memory chip of claim 1, wherein the interface circuit is configured to output the repeat request signal as a multibit signal. The semiconductor memory chip of claim 3, wherein the interface circuit outputs the repeat request signal in coded fashion.

4. A semiconductor memory module comprising a plurality of semiconductor memory chips, each semiconductor memory chip comprising an interface circuit configured to receive write data and to detect a transmission error in a received write datum, wherein, upon detection of a transmission error in the write data by an interface circuit, each interface circuit is configured to output, via a separate request signal path, a repeat request signal for the repeated transmission of a write datum detected as erroneous.

5. The semiconductor memory module of claim 4, wherein each request signal path is led as an individual signal line separately to a respective external contact of the semiconductor memory module.

6. The semiconductor memory module of claim 4, wherein each request signal path is led from a respective interface circuit as an individual signal line to an OR circuit on the semiconductor memory module, the output signal of the OR circuit being passed via an individual signal line to a terminal contact of the semiconductor memory module.

7. The semiconductor memory module of claim 4, wherein the request signal is passed by each semiconductor memory chip as a multibit signal.

8. The semiconductor memory module of claim 7, wherein each interface circuit is further configured to output the repeat request signal in coded fashion.

9. A method for transmitting write data to a semiconductor memory chip, the method comprising:

transmitting write data to the semiconductor chip externally via a data transmission path;

detecting a transmission error in the received write datum; and

upon detection of a transmission error in the received write datum, outputting a repeat request signal for the repeated transmission of a write datum detected as erroneous via a separate request signal path from the semiconductor memory chip.

10. The method of claim 9, wherein the repeat request signal is output as a single-bit signal.

11. The method of claim 9, wherein the repeat request signal is output as a multibit signal.

12. The data transmission method as claimed in claim 11, wherein the repeat request signal is output in coded fashion.

13. A method for transmitting write data to a plurality of semiconductor memory chips arranged on a semiconductor memory module, the method comprising:

transmitting write data to at least one of the semiconductor memory chips externally via a data transmission path;

in each semiconductor memory chip, checking a received write datum and detecting a transmission error; and

upon detection of a transmission error in each semiconductor memory chip, outputting a repeat request signal for the repeated transmission of the write datum detected as erroneous via a separate request signal path from the respective semiconductor chip.

14. The method of claim 13, wherein the repeat request signal of each semiconductor memory chip is output from each semiconductor memory chip as a single-bit signal.

15. The method of claim 13, wherein the repeat request signal of each semiconductor memory chip is passed from each semiconductor memory chip separately to a respective terminal contact of the semiconductor memory module.

16. The method of claim 13, wherein each of the repeat request signals is passed from the respective semiconductor memory chip on the semiconductor circuit module as a single-bit signal to an individual terminal contact of the semiconductor memory module.

17. The method of claim 13, wherein the repeat request signal of each semiconductor memory chip is output from the respective semiconductor memory chip as a multibit signal.

18. The method of claim 17, wherein the repeat request signal of each semiconductor memory chip is output in coded fashion.