Method and apparatus for full-chip thermal analysis of semiconductor chip designs

• US 20060095876A1
• Filed: 11/03/2004
• Published: 05/04/2006
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Keysight Technologies, Inc.
• Original Assignee: Gradient Design Automation, Inc.
• Inventors: Chandra, Rajit
• Granted Patent: US 7,194,711 B2
• Time in Patent Office: Days
• US Class Current: 716/115
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method and apparatus for full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal analysis of a semiconductor chip design comprises receiving at least one input relating to a semiconductor chip design to be analyzed. The input is then processed to produce a three-dimensional thermal model of the semiconductor chip design. In another embodiment, thermal analysis of the semiconductor chip design is performed by calculating power dissipated by transistors and interconnects included in the semiconductor chip design and distributing power dissipated by the interconnects.

Claims

1. A method for performing thermal analysis of a semiconductor chip design, the method comprising:

receiving at least one input relating to said semiconductor chip design; and

processing said at least one input to produce a full-chip thermal model of said semiconductor chip design.

2. The method of claim 1, wherein said at least one input comprises at least one of design data and library data.

3. The method of claim 2, wherein said design data comprises industry standard design data.

4. The method of claim 2, wherein said design data comprises at least one of electrical component extraction data, extracted parasitic data, design representations, layout data, techfiles describing layer information or package models, power tables and associated switching data.

5. The method of claim 2, wherein said library data comprises data relating to one or more semiconductor devices, one or more interconnects, or one or more semiconductor devices and one or more interconnects incorporated in said semiconductor chip design.

6. The method of claim 5, wherein at least one of said one or more semiconductor devices is a transistor.

7. The method of claim 1, wherein said processing step comprises:

calculating power dissipated by at least one of one or more semiconductor devices and one or more interconnects incorporated in said semiconductor chip design; and

distributing power dissipated by distributing power dissipated by at least one of said one or more interconnects, said one or more semiconductor devices, and between said one or more interconnects and said one or more semiconductor devices to produce a three-dimensional thermal model.

8. The method of claim 7, wherein said method is implemented for a steady state thermal analysis.

9. The method of claim 7, wherein said method is implemented to account for interdependent heat fields between said one or more semiconductor devices and said one or more interconnects.

10. The method of claim 7, wherein said power dissipated by said one or more semiconductor devices and said one or more interconnects is calculated based on pre-characterized semiconductor device and interconnect parameters working at at least one of semiconductor device, cell and block level circuit levels.

11. The method of claim 7, wherein said method is implemented for a transient analysis.

12. The method of claim 7, further comprising the step of:

dynamically simulating a circuit embodied in said semiconductor chip design.

13. The method of claim 12, wherein said power dissipated by said one or more semiconductor devices and said one or more interconnects is calculated based on said simulated circuit.

14. The method of claim 7, wherein said dissipated power is distributed in said one or more interconnects based on one or more electrical properties of said one or more interconnects.

15. The method of claim 14, wherein said one or more electrical properties include resistances.

16. The method of claim 1, wherein said full-chip thermal model is modeled by:

partitioning, in at least one dimension, volumes of steep temperature gradients over said semiconductor chip design; and

determining temperatures for said partitioned volumes.

17. The method of claim 1, where said full-chip thermal model is a three-dimensional thermal model.

18. A computer readable medium containing an executable program for performing thermal analysis of a semiconductor chip design, where the program performs the steps of

receiving at least one input relating to said semiconductor chip design;

and

processing said at least one input to produce a full-chip thermal model of said semiconductor chip design.

19. The computer readable medium of claim 18, wherein said at least one input comprises at least one of design data and library data.

20. The computer readable medium of claim 19, wherein said design data comprises industry standard design data.

21. The computer readable medium of claim 19, wherein said design data comprises at least one of electrical component extraction data, extracted parasitic data, design representations, layout data, techfiles describing layer information or package models, power tables and associated switching data.

22. The computer readable medium of claim 19, wherein said library data comprises data relating to one or more semiconductor devices, one or more interconnects, or one or more semiconductor devices and one or more interconnects incorporated in said semiconductor chip design.

23. The computer readable medium of claim 22, wherein at least one of said one or more semiconductor devices is a transistor.

24. The computer readable medium of claim 18, wherein said processing step comprises:

calculating power dissipated by at least one of one or more semiconductor devices and one or more interconnects incorporated in said semiconductor chip design; and

distributing power dissipated by at least one of said one or more interconnects, said one or more semiconductor devices, and between said one or more interconnects and said one or more semiconductor devices to produce a three-dimensional thermal model.

25. The computer readable medium of claim 24, wherein said method is implemented for a steady state thermal analysis.

26. The computer readable medium of claim 24, wherein said method is implemented to account for interdependent heat fields between said one or more semiconductor devices and said one or more interconnects.

27. The computer readable medium of claim 24, wherein said power dissipated by said one or more semiconductor devices and said one or more interconnects is calculated based on pre-characterized semiconductor device and interconnect parameters working at at least one of semiconductor device, cell and block level circuit levels.

28. The computer readable medium of claim 24, wherein said method is implemented for a transient analysis.

29. The computer readable medium of claim 24, further comprising the step of:

dynamically simulating a circuit embodied in said semiconductor chip design.

30. The computer readable medium of claim 29, wherein said power dissipated by said one or more semiconductor devices and said one or more interconnects is calculated based on said simulated circuit.

31. The computer readable medium of claim 24, wherein said dissipated power is distributed in said one or more interconnects based on one or more electrical properties of said one or more interconnects.

32. The computer readable medium of claim 31, wherein said one or more electrical properties include resistances.

33. The computer readable medium of claim 18, wherein said full-chip thermal model is modeled by:

partitioning, in at least one dimension, volumes of steep temperature gradients over said semiconductor chip design; and

determining temperatures for said partitioned volumes.

34. The computer readable medium of claim 18, where said full-chip thermal model is a three-dimensional thermal model.

35. Apparatus for performing thermal analysis of a semiconductor chip design, the apparatus comprising:

means for receiving at least one input relating to said semiconductor chip design; and

means for processing said at least one input to produce a full-chip thermal model of said semiconductor chip design.

36. A method for performing thermal analysis of a semiconductor chip design, the method comprising:

calculating or receiving information pertaining to power dissipated by at least one of one or more semiconductor devices and one or more interconnects included in said semiconductor chip design; and

distributing power dissipated by at least one of said one or more interconnects, said one or more semiconductor devices, and between said one or more interconnects and said one or more semiconductor devices.

37. The method of claim 36, wherein said method is implemented for a steady state thermal analysis.

38. The method of claim 36, wherein said method is implemented to account for interdependent heat fields between said one or more semiconductor devices and said one or more interconnects.

39. The method of claim 36, wherein said power dissipated by said one or more semiconductor devices and said one or more interconnects is calculated based on pre-characterized semiconductor device and interconnect parameters working at at least one of semiconductor device, cell and block level circuit levels.

40. The method of claim 39 wherein said pre-characterized semiconductor device and interconnect parameters comprise at least one of design data and library data.

41. The method of claim 40, wherein said design data comprises industry standard design data.

42. The method of claim 40, wherein said design data comprises at least one of electrical component extraction data, extracted parasitic data, design representations, layout data, techfiles describing layer information or package models, power tables and associated switching data.

43. The method of claim 40, wherein said library data comprises data relating to said one or more semiconductor devices and said one or more interconnects incorporated in said semiconductor chip design.

44. The method of claim 43, wherein at least one of said semiconductor devices is a transistor.

45. The method of claim 36, wherein said method is implemented for a transient analysis.

46. The method of claim 36, further comprising the step of:

dynamically simulating a circuit embodied in said semiconductor chip design.

47. The method of claim 46, wherein said power dissipated by said one or more semiconductor devices and said one or more interconnects is calculated based on said simulated circuit.

48. The method of claim 36, wherein said dissipated power is distributed in said one or more interconnects based on one or more electrical properties of said one or more interconnects.

49. The method of claim 48, wherein said one or more electrical properties include resistances.

50. The method of claim 36, further comprising the step of:

modeling a three-dimensional thermal model of said semiconductor chip design based on said calculated and distributed power.

51. The method of claim 50, wherein said modeling step comprises:

partitioning, in at least one dimension, volumes of steep temperature gradients over said semiconductor chip design; and

determining temperatures for said partitioned volumes.

52. A computer readable medium containing an executable program for performing thermal analysis of a semiconductor chip design, where the program performs the steps of

calculating or receiving information pertaining to power dissipated by at least one of one or more semiconductor devices and one or more interconnects included in said semiconductor chip design;

and

distributing power dissipated by at least one of said one or more interconnects, said one or more semiconductor devices, and between said one or more interconnects and said one or more semiconductor devices.

53. The computer readable medium of claim 52, wherein said method is implemented for a steady state thermal analysis.

54. The computer readable medium of claim 52, wherein said method is implemented to account for interdependent heat fields between said one or more semiconductor devices and said one or more interconnects.

55. The computer readable medium of claim 52, wherein said power dissipated by said one or more semiconductor devices and said one or more interconnects is calculated based on pre-characterized semiconductor device and interconnect parameters working at at least one of semiconductor device, cell and block level circuit levels.

56. The computer readable medium of claim 55 wherein said pre-characterized semiconductor device and interconnect parameters comprise at least one of design data and library data.

57. The computer readable medium of claim 56, wherein said design data comprises industry standard design data.

58. The computer readable medium of claim 56, wherein said design data comprises at least one of electrical component extraction data, extracted parasitic data, design representations, layout data, techfiles describing layer information or package models, power tables and associated switching data.

59. The computer readable medium of claim 56, wherein said library data comprises data relating to said one or more semiconductor devices and said one or more interconnects incorporated in said semiconductor chip design

60. The computer readable medium of claim 59, wherein at least one of said one or more semiconductor devices is a transistor.

61. The computer readable medium of claim 52, wherein said method is implemented for a transient analysis.

62. The computer readable medium of claim 52, further comprising the step of:

dynamically simulating a circuit embodied in said semiconductor chip design.

63. The computer readable medium of claim 62, wherein said power dissipated by said one or more semiconductor devices and said one or more interconnects is calculated based on said simulated circuit.

64. The computer readable medium of claim 52, wherein said dissipated power is distributed in said one or more interconnects based on one or more electrical properties of said one or more interconnects.

65. The method of claim 64, wherein said one or more electrical properties include resistances.

66. The computer readable medium of claim 52, further comprising the step of:

modeling a three-dimensional thermal model of said semiconductor chip design based on said calculated and distributed power.

67. The computer readable medium of claim 66, wherein said modeling step comprises:

partitioning, in at least one dimension, volumes of steep temperature gradients over said semiconductor chip design; and

determining temperatures for said partitioned volumes.

68. Apparatus for performing thermal analysis of a semiconductor chip design, the apparatus comprising:

means for calculating power dissipated by one or more semiconductor devices, one or more interconnects, or one or more semiconductor devices and one or more interconnects included in said semiconductor chip design; and

means for distributing power dissipated by at least one of said one or more interconnects, said one or more semiconductor devices, and between said one or more interconnects and said one or more semiconductor devices.