Architecture and interconnect scheme for programmable logic circuits
First Claim
1. An integrated circuit, comprising:
- a first region comprising;
a first plurality of cells located along a first dimension and a second dimension, wherein the first region has a first span along the first dimension and a second span along the second dimension;
a plurality of switches; and
a first plurality of conductors located within the first region, wherein each conductor of the first plurality of conductors to selectively couple to the inputs and outputs of cells of the first plurality of cells and conductors of the first plurality of conductors through the plurality of switches and wherein the first plurality of conductors span cells of the first plurality of cells along the first dimension and the second dimension, wherein the first plurality of conductors comprises;
a first conductor having a first span along the first dimension;
a second conductor having a second span along the first dimension;
a third conductor having a third span along the second dimension; and
a fourth conductor having a fourth span along the second dimension;
wherein the first span of the first region is greater than the first span of the first conductor and the first span of the first conductor is greater than the second span of the second conductor, wherein the second span of the first region is greater than the third span of the third conductor and the third span of the third conductor is greater than the fourth span of the fourth conductor;
a second region located within the first region, having a span along the first dimension, comprising;
a subgroup of cells of the first plurality of cells located in the second region, wherein the span of the second region is less than the second span of the second conductor;
a fifth conductor of the first plurality of conductors located within the second region having a fifth span equal to the span of the second region along the first dimension; and
a first cell of the first plurality of cells;
a second cell of the first plurality of cells;
two independently program controlled switches comprising a first switch and a second switch, wherein the first cell is configured to selectively couple to drive the fifth conductor through at least the first switch and wherein the second cell is configured to selectively couple to drive the fifth conductor through at least the second switch.
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Abstract
An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.
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Citations
30 Claims
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1. An integrated circuit, comprising:
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a first region comprising;
a first plurality of cells located along a first dimension and a second dimension, wherein the first region has a first span along the first dimension and a second span along the second dimension;
a plurality of switches; and
a first plurality of conductors located within the first region, wherein each conductor of the first plurality of conductors to selectively couple to the inputs and outputs of cells of the first plurality of cells and conductors of the first plurality of conductors through the plurality of switches and wherein the first plurality of conductors span cells of the first plurality of cells along the first dimension and the second dimension, wherein the first plurality of conductors comprises;
a first conductor having a first span along the first dimension;
a second conductor having a second span along the first dimension;
a third conductor having a third span along the second dimension; and
a fourth conductor having a fourth span along the second dimension;
wherein the first span of the first region is greater than the first span of the first conductor and the first span of the first conductor is greater than the second span of the second conductor, wherein the second span of the first region is greater than the third span of the third conductor and the third span of the third conductor is greater than the fourth span of the fourth conductor;
a second region located within the first region, having a span along the first dimension, comprising;
a subgroup of cells of the first plurality of cells located in the second region, wherein the span of the second region is less than the second span of the second conductor;
a fifth conductor of the first plurality of conductors located within the second region having a fifth span equal to the span of the second region along the first dimension; and
a first cell of the first plurality of cells;
a second cell of the first plurality of cells;
two independently program controlled switches comprising a first switch and a second switch, wherein the first cell is configured to selectively couple to drive the fifth conductor through at least the first switch and wherein the second cell is configured to selectively couple to drive the fifth conductor through at least the second switch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of operating an integrated circuit, comprising:
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providing a first region comprising a first plurality of cells located along a first dimension and a second dimension, wherein each of the first plurality of cells has an input and an output, and wherein the first region has a first span along the first dimension and a second span along the second dimension;
providing a plurality of switches in the first region;
providing a first plurality of conductors located within the first region, wherein the first plurality of conductors comprises a first conductor having a first span along the first dimension, a second conductor having a second span along the first dimension, a third conductor having a third span along the second dimension and a fourth conductor having a fourth span along the second dimension;
selectively coupling each of the first plurality of conductors to the inputs and outputs of cells of the first plurality of cells and conductors of the first plurality of conductors through switches;
wherein the first span of the first region is greater than the first span of the first conductor and the first span of the first conductor is greater than the second span of the second conductor;
wherein the second span of the first region is greater than the third span of the third conductor and the third span of the third conductor is greater than the fourth span of the fourth conductor;
providing a second region, located within the first region, having a span along the first dimension, comprising a subgroup of cells of the first plurality of cells, wherein the span of the second region is less than the second span of the second conductor along the first dimension;
providing a fifth conductor of the first plurality of conductors in the second region having a fifth span equal to the span of the second region along the first dimension;
providing a first cell and a second cell of the first plurality of cells and two independently program controlled first switch and second switch in the first region;
selectively coupling the first cell to drive the fifth conductor through at least the first switch; and
selectively coupling the second cell to drive the fifth conductor through at least the second switch. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification